by kamalnadh
1) Threshold voltage depends on
a) Temperature.
b) Doping concentration.
c) Oxide thickness.
d) All.
2) Temperature inversion is
a) Delay increase in higher technologies and decreases in lower technologies.
b) Delay increase in lower technologies and decrease in higher technologies.
c) Maintain the constant delay in high and low technologies.
d) None.
5) Delay between shortest path and longest path in the clock is called......
6) HVT cell has
7) FRAM view has
8) Clock gating is used to reduce
9) Tap cells are used
10) HFNS is used
11) To detect manufacturing faults in macros we use
12) Cross-talk can be avoided by...
13) CRPR stands for...
14) what are the pre routing in the design
15) Which configuration is more preferred during floor planning
d) Blockages.
20) End cap cell is used
21) HFNS is used at the stage of
d) None.
23) Which of the following metal layer has max resistance
24) Chip utilization depends on..........
25) To achieve better timing.......cell are placed in critical path
41) In soft blockage........cells are placed
42) More IR drop due to...
d) None
61) If arrival time is more than required time______violations will come
69) Maximum current density of metal is available in....
d) None.
74) No.of tracks in high metal layer will be..... tracks in low metal layer
a) Less than.
b) More than.
c) Equal to.
75. Which is not preferred for clock buffers
a) SVT.
b) LVT.
c) HVT.
d) None
76. Placement blockage is created at the stage of floor plan
a) True
b) False
77. Abutted design has
a) No gap between blocks.
b) Gap between the blocks.
c) Both A&B.
d) None
78. In power planning stage rings are placed
a) In middle of core.
b) Around the core.
c) At corner.
d) None
79. Scan chain re ordering will reduce congestion
a) True
b) False
80. Static power can be reduced by placing
a) LVT cells
b) SVT cells
c) HVT cells
81. Dynamic power consumption can be reduced by
a) Load capacitance.
b) Cell sizing.
c) Load sharing.
d) All of the above.
82. CTO can be performed by
a) Buffering.
b) Gate sizing.
c) Both A&B.
d) None
3) Uncertainty is more in
a) Hold.
b) Setup.
c) Both A&B.
4) If gate area is less than metal area then it leads to
a) Antenna violations.
b) Electromigration.
c) Congestion.
d) None.
a) Global skew.
b) Useful skew.
c) Local skew.
d) Slack.
a) Slower and more leakage power.
b) Faster and more leakage power.
c) Slower and less leakage power.
d) Faster and less leakage power.
a) Layout information and used at the time of tape-out.
b) Layout information and used in place&route.
c) Abstract view and used in place and route.
d) Abstract view and used at the time of tape-out.
a) Static power dissipation.
b) Dynamic power dissipation.
c) Short circuit current.
a) To avoid the dynamic IR drop.
b) To connect the gap between cells.
c) To avoid dynamic power dissipation.
d) To avoid latch up problem.
a) To balance the timing.
b) To balance the power.
c) To balance the load.
d) None.
a) JTAG (joint test action group).
b) MBIST (macro built in self test).
c) LVS.
d) All.
12) Cross-talk can be avoided by...
a) Using low metal layers.
b) Using long nets.
c) Decreasing the spacing between the metal layers.
d) Shielding the nets.
a) Clock reconvergence past removal.
b) Cell reconvergence pessimism removal.
c) Clock reconvergence pessimism removal.
d) Clock reconvergence present removal.
a) Signal routing.
b) Power routing.
c) Signal and power routing.
d) None.
a) With channel spacing between rows and no double back.
b) Double back with non flipped rows.
c) With channel spacing between rows and no double back.
d) Double back with flipped rows.
16) Which gate is most preferred in the design
a) NOR.
b) NAND.
c) AND.
d) XOR.
17) Elecromigration can be reduced by
a) Increasing the width.
b) Increasing the spacing between nets.
c) Both A&B.
18) I/O delays are more than cell delay
a) True.
b) False.
19) Major importance of power plan is
a) IR drop.
b) Electromigration.
c) Congestion.
d) Both A&B.
20) End cap cell is used
a) To avoid the dynamic IR drop.
b) To avoid cell damage at the end of row.
c) To avoid dynamic power dissipation.
d) To connect the gap between cells.
21) HFNS is used at the stage of
a)CTS.
b) Placement.
c) Routing.
d) Floor plan.
22) Virtual clock is
a) Logically not connected.
b) Physically doe't exist.
c) Both a&b.
a) Metal 3.
b) Metal 5.
c) Metal 2.
d) Metal 6.
a) Only standard cells.
b) Standard cells and macros.
c) Only macros.
d) Standard cells,macros,I/0 pads.
a) HVT
b) LVT
c) SVT
26) Delay of cell depends on____
27) Clock tree does't contain following cell....
28) What is the effect of high drive strength buffer when added in long net
a) Input transition and output load.
b) Output transition and input load.
c) Output transition and output load.
d) Input load and output transition.
a) Clock buffer.
b) AOI cell.
c) Clock inverter.
d) None.
a) Delay on net decreases.
b) Capacitance on net increases.
c) Delay on net increases.
d) Distance on the net increases.
29) LVT cell has
a) Faster and more leakage power.
b) Slower and more leakage power.
c) Faster and less leakage power.
d) Slower and less leakage power.
30) Cell view has
31) Jitter is the
a) Layout information and used at the time of tape out.
b) Abstract view and used in place and route.
c) Layout information and used in place&route.
d) Abstract view and used at the time of tape out.
a) Difference between two clock pulses.
b) Ratio of input transition and output load.
c) Deviation of clock edge from its ideal position.
d) Difference between required time-arrival time.
32) Decap cell is used
33) Hard macro is
a) To avoid the dynamic IR drop.
b) To avoid cell damage at the end of row.
c) To avoid dynamic power dissipation.
d) To connect the gap between cells.
a) Circuit is fixed,we know only timing information and don't know the functional information.
b) Circuit is not fixed,we know the timing and functional information.
c) Circuit is fixed,we don't know the timing and functional information.
d) Circuit is fixed,we know the timing and functional information.
34) Which design is more complicated
a) 500mhz.
b) 54mhz.
c) 500khz.
d) 650mhz.
35) Clock skew can be minimized by
a) Buffering the clock.
b) Add delay in data path.
c) Clock reversing.
d) A&C.
e) A,B&C.
36) FPGA chip is
a) Simple in design.
b) It can be re programmed.
c) Manufacturing time is less.
d) A&C.
e) A,B&C.
37) Capacitance table can be created by
a) .tf file
b) .lib file
c) lef file
d) .sdc
38) To detect manufacturing faults in I/O we use
a) JTAG (joint test action group).
b) MBIST (macro built in self test).
c) LVS
d) All
39) ASIC chip is
a) Simple in design.
b) Manufacturing time is less.
c) It is faster.
d) Both A&C.
40) Use of placement blockage is
a) Block the cells in specific area.
b) Reduce the congestion.
c) Defines std cell area.
d) A&B.
e) A,B&C.
a) No cells.
b) Only buffers and inverters.
c) Only sequential cells.
d) Any cells.
a) Increase in metal width.
b) Decrease in metal length.
c) Lot of metal layers.
d) Increase in metal length.
43) To avoid cross-talk the shielding net is usually connected to____
44) Which of the following is preferred while placing macros
a) VDD.
b) clock.
c) VDD and VSS.
d) VSS.
a) Macros placed left and right side of die.
b) Macros placed center of the die.
c) Macros placed top and bottom side of die.
d) Macros placed based on the connectivity of the I/O.
45) Pitch of the wire is______
a) Min width.
b) Min width+min spacing.
c) Min spacing.
d) Min width-min spacing.
46) In 9 metal layer design which metal layer you will use for power
47) After the final routing the violations in the design
48) JTAG cell is used
a) Metal 5 and metal 6.
b) Metal 6 and metal 7.
c) Metal 8 and metal 9.
d) Metal 4 and metal 5.
a) There can be hold violations but not setup violations.
b) There can be both violations.
c) There can be setup violations but not hold violations.
d) There can be no setup and no hold violations.
a) To check the io connectivity.
b) To avoid cell damage at the end of row.
c) To avoid dynamic power dissipation.
d) To connect the gap between cells.
49) Soft macro is
a) Circuit is fixed,we know only timing information and don't know the functional information.
b) Circuit is not fixed,we know the timing and functional information.
c) Circuit is fixed,we don't know the timing and functional information.
d) Circuit is fixed,we know the timing and functional information.
50) Latch-up problem can be reduced by
a) Increasing the spacing.
b) Increase the doping concentration.
c) Use of guard rings.
d) All
51) Antenna problem can be caused by
a) Increasing the net length.
b) Decreasing the net length.
c) Increasing the load.
d) None.
52) Cross-talk can be reduced by
a) Increasing the spacing between nets.
b) Shielding.
c) Decreasing the spacing between nets.
d) Both A&B.
53) FPGA stands for
a) Field programmable gate array.
b) Fixed programmable gate arrangement.
c) Fixed programmable gate array.
54) Pre-routing means routing of.....
a) Clock nets.
b) Signal nets.
c) IO nets.
d) PG nets.
55) Hold is fixed....
a) Before CTS.
b) Before placement.
c) After CTS.
d) After placement.
56) Which of the following is best suited for CTS
a) Buffer.
b) Clk buffer.
c) Inverter.
d) Clk inverter.
57) Routing congestion is___
a) Available tracks are less than required tracks.
b) Depends on the routing layers available.
c) Required tracks are less than available tracks.
d) None.
58) Halo allows the placement of
a) Only standard cells.
b) Only macros.
c) Only buffers and inverters.
d) None.
59) Aspect ratio is
a) Width /height.
b) Height/width.
c) Width+height.
d) Width -height.
60) What is the goal of CTS
a) Minimum EM.
b) Minimum slack.
c) Minimum skew.
d) Minimum IR drop.
a) Setup.
b) Hold.
c) Both.
d) None.
62) Maximum voltage drop will be there at(without macros)......
63) The solution of antenna effect is.....
64) Which of the following is not present in SDC file
a) Right and left side.
b) Middle.
c) Top and bottom side.
d) None.
a) Shielding.
b) Buffer insertion.
c) Diode insertion.
d) Double spacing.
64) Which of the following is not present in SDC file
a) Max transition.
b) Max current density.
c) Max capacitance.
d) Max fan out.
65) Which is the following is not present in logical DRC's
a) Max transition.
66) Congestion can be reduced by
b) Shorts.
c) Max fan-out.66) Congestion can be reduced by
a) Adjusting the cell density in congested area.
b) Using proper blockage.
c) Both A&B.
d) None.
67) The metal area and(or)perimeter of conducting layer/gate to gate area is called...
a) Aspect ratio.
b) OCV.
c) Antenna ratio.
d) Utilization.
68) search and repair is used for.....
a) Reduce EM violations.
b) Reduce IR drop.
c) Reduce DRC.
d) None.
69) Maximum current density of metal is available in....
a) .lib
b) .tf
c) .lef
d) .sdc
70) Dynamic power consumption can be reduced by
a) Reduce voltage swing in all nodes.
b) Reduce the load capacitance.
c) Both A&B.
71) what violations solved in LVS
a) Shorts.
b) Opens.
c) Missing text layers.
d) All.
72) Utilization of chip after placement optimization will be_
a) Decreases.
b) Constant.
c) Increases.
d) None.
73) Routing congestion can be avoided by.......
a) Distributing cells.
b) Placing cells closer.
c) Placing cells at corners.
d) None.
a) Less than.
b) More than.
c) Equal to.
75. Which is not preferred for clock buffers
a) SVT.
b) LVT.
c) HVT.
d) None
76. Placement blockage is created at the stage of floor plan
a) True
b) False
77. Abutted design has
a) No gap between blocks.
b) Gap between the blocks.
c) Both A&B.
d) None
78. In power planning stage rings are placed
a) In middle of core.
b) Around the core.
c) At corner.
d) None
79. Scan chain re ordering will reduce congestion
a) True
b) False
80. Static power can be reduced by placing
a) LVT cells
b) SVT cells
c) HVT cells
81. Dynamic power consumption can be reduced by
a) Load capacitance.
b) Cell sizing.
c) Load sharing.
d) All of the above.
82. CTO can be performed by
a) Buffering.
b) Gate sizing.
c) Both A&B.
d) None
Answers:-
1) D
2) A
3) B
4) A
5) A
6) C
7) C
8) B
9) D
10) C
11) B
12) D
13) C
14) B
15) D
16) B
17) A
18) A
19) D
20) B
21) B
22) C
23) C
24) B
25) B
26) A
27) B
28) A
29) A
30) A
31) C
32) A
33) A
34) D
35) E
36) E
37) C
38) A
39) C
40) C
41) B
42) D
43) D
44) D
45) B
46) C
47) B
48) A
49) B
50) D
51) A
52) D
53) A
54) D
55) C
56) B
57) A
58) C
59) B
60) C
61) A
62) B
63) C
64) B
65) B
66) C
67) C
68) C
69) B
70) C
71) D
72) C
73) A
74) A
75) C
76) A
77) A
78) B
79) A
80) C
81) D
82) C
75) C
76) A
77) A
78) B
79) A
80) C
81) D
82) C
83)
84)
