STA basic questions and answers

    by Kamalnadh

Q 1. what is STA?
A:  It is a method to determine  the timing constrains of a circuit without simulations.

Q 2. What is setup time?
A: The minimum time required for the data to be stable before the clock edge.

Q 3. What is hold time?

A: The minimum time required for the data to be stable after the clock edge.

Q 4. What is arrival time?
A: This is the time required for data travel through data path.

Q 5. What is required time?
A: It is the time taken for the clock to travel through the clock path.

Q 6. What is slack?

A: It is the difference between the required time and arrival time.

              Slack = Required time­­ - Arrival time

             Setup slack = Required time – Arrival time

             Hold slack = Arrival time – Required time

Q 7.What are the data paths in STA?
A: a) Input port to register.
b) Register to register.
c) Register to output port.
d) Input port to output port.

Q 8. What are the timing constraints (or)exceptions?
 A: a) False path:- It specifies the logic path.
b) multi cycle path:- It specifies the no.of  clock cycles required to propagate data from the start to the end of the path.
c)min/max delay:- It over ride the default setup and hold constraints with specific max &min time values.

Q 9. What is latency (or) clock network delay (or) insertion delay?

A: It is the total delay that a clock signal travels from clock source to clock pin of the flip flop.

Q 10.  What is clock skew?

A: It is the instantaneous difference between the two clock network delays.

Q 11. What is uncertainty?
A: Deviation of clock edge from it’s ideal position.it is caused due to jitters.

Q 12. What is cell delay (or) propagation delay?

A: It is the amount of delay from input to output in a logic path.

Q 13. What is net delay?

A: It is the amount of delay from the output of the cell to the input of the next cell in the timing path.

Q 14. What is drive strength?

A: It is the relative capability to charge/discharge the capacitance present at it’s output (or) It is the capacity of a cell to drive a value to the cell connected to it’s output.It is easy to drive small cell than large.

Q 15. What is clock gating?

A: It is a popular technique used in many synchronous circuits for reducing dynamic power dissipation.It saves power by adding more logic to a circuit to prune the clock tree. 

Q 16. What is OCV (on chip variation)?

A: Flate derate is applied  to make fast path more fast & slow path more slow.Delay vary across a single die due to P,V,T .this to be modeled by scaling the coefficients. 

Q 17. Why we need STA?

A: Sta provides  faster & simpler way of checking & analyzing all the timing parts in the design for any timing violations.

Q 18. What is global skew?

A: It is the difference in the arrival of clock signal at the clock pin of non related flip flops.

Q 19. What is useful skew? 

A: If the clock skew is intentionally added to meet timing then it is called useful skew.

Q 20. What is local skew?

A: It is the difference in the arrival of clock signal at the clock pin of related flip flops.

Q 21. What is derating?
A: Timing derating factor model the effects of varying operating conditions by adjusting the delay values calculated for the individual timing arc of a block.

Q 22. What is CRPR (clock re convergence pessimism removal)?

A: It can be used to remove this pessimism &remove penalty by using the common cell for both launch &capture flip flop.

Q 23. What is recovery time?
A: It is the minimum time that an asynchronous control input pin must be stable after being deserted & before the next clock transition.

Q 24. What is removal time?
A:  It is the minimum time that the asynchronous control input pin must be stable before being deserted & after the previous clock transition.

Q 25. What is the minimum clock pulse width?

A: The amount of time after rising edge of a clock that the clock signal of a clocked device must remain stable.

Q 26. What are the advantages of STA?

A: a) Speed is more.

b) Capacity to handle full chip.
c) Exhaustive timing coverage.
d) Vectors are not required.

e) Suitable for large designs.

Q 27. What are the disadvantages of STA?

A: a) Results are pessimistic .
b) Must define timing requirements/exceptions.

c) Difficulty in handling asynchronous designs.

Q 28. What are the libraries in STA?

A: a) Link lib:- it is a reference path.

b) Target lib:- it is used for optimization.
c) Symbolic lib:- it having symbols of cells(gates).
d) Synthetic lib:- AOI ,OAI combinations.
e) Design ware lib:- provides the connectivity path.

f) Physical lib:- it have shape of cell.

Q 29. What is DRC (design rule check)?

A: It is the area of electronic design automation that determines whether the physical layout of a particular chip layout satisfy a series of recommended parameters called rules.

Q30. What are the types of DRC’s?

A: a) Logical DRC's:- max transition, max capacitance,max fan out.
b) Physical DRC's:- short, open,spacing rules,overlap.

Q 31. What is LVS (layout versus schematic)?

A: LVS is another major check in the physical verification stage.Here you are verifying that whether a particular IC layout correspond to the original schematic or circuit diagram of design.

Q 32. What is cross talk?

A: It is the undesirable electrical interaction between two or more physical adjust nets due to the capacitance cross coupling.

Q 33. What is wire load model?
 A: It is the synthesis phase to account for the physical delay.It contains a lookup table that gives wire resistance ,wire capacitance and the area per unit length.That can be interpolated from the fanout.

Q 34.What is virtual clock?

A: It will help to reduce the timing delay of overall operation.It is the clock which is logically not connected to any port of the design and physically doesn’t exist.It is during optimization.

Q 35.Is zero skew is possible?

A: it is not possible because of all flip flops are not getting the same clock.

Q 36. How to fix setup and hold violations?

A: Fixing setup:-

• Reduce the amount of buffers in the path.
• Replace buffer with 2 inverters.
• Change HVT cells to SVT/LVT cells.
• Increase the drive strength.
• Insert repeaters.
• Adjusting cell position in layout.

 Fixing hold:-

• By adding delay in the path.
• Decreasing the size of certain cells in the data path.

Q 37. What is MMMC (multi mode multi corner)?
A: A view is a combination of a mode & corner that is required for a particular timing check such as setup and hold.

Q 38. What is mode and corner?

A: Mode:- it is a set of clocks,supply voltage,timing constraints and library.it also have sdf.
Corner:- it is defined as a set of libraries characterized for process,voltage, temperature variations.

Q 39. How to minimize the skew?

A: a) Buffering the clock.

     b) Add delay in data path.

     c) Clock reversing.