by kamalnadh
Q 1.What is physical design?
A. The physical design is the process of transforming a circuit description into the physical layout which describes position of the cells and routs for the interconnections between them.
Q 2.which design is more complicated 10MHZ or 100MHz?
A. 100mhz. because high frequency means low time period.So it is difficult to handle the violations in low time period.
Q 3.what is floor planing?
A. The floor plan is a process of determining the macro placement,power grid generation and I/O placement.
Q 4.If you have both IR drop and congestion how will you fix it?
A. a) Spreed macros.
b) Spreed standard cells.
c) Increase strap width.
d) Increase no.of straps.
e) Use proper blockage.
Q 5.What are the Tie-high and Tie-low cells?
A. These are used to connect the gate of transistor to either power or ground.It avoid direct connection between power and gate of transistor.
Tie-high:- One terminal is connected to vdd and another terminal is connected to gate of transistor.
Tie-low:- One terminal is connected to vss and another terminal is connected to gate of transistor.
Q 6.What are the checks to be done before cts?
A. a) Placement -completed.
b) Power ground nets -pre-routed.
c) Estimated congestion -acceptable.
d) Estimated timing -acceptable.
e) Estimated max transition/capacitance -no violations.
f) High fan-out nets.
Q 7.What are the power gating cells?
A. The power gating is to avoid static power dissipation.The power gating cells are
a) Power switches.
b) Level sifters.
c) Retention registers.
d) Isolation cells.
e) Power controller.
Q 8.What is HFNS(high fan-out net synthesis)?
A. HFNS is the process of buffering the high fan-out nets to balance the load.
Q 9.Where HFNS is used?
A. Generally at placement stage HFNS is performed.it is also performed at synthesis step using design compiler.
Q 10.What is Electromigration(EM)?
A. When high current density continuously flows through a metal due to the high current the atoms moving with kinetic energy and they transfer the energy to another atoms and increases the temperature due to these the metal will damage.
Q 11.Is zero skew is possible?
A. Practically it is not possible because all the flip flops are not getting the same clock.The skew is exist when the two different clocks are present.Zero skew means all clocks are same practically it is not possible.
Q 12.How to reduce latchup problem?
A. a) Increase spacing between p-well and n-well.
b) Increase well/substrate doping concentration.
c) Use ground rings around device.
Q 13.What are the check list after cts?
A. a) Skew report.
b) Clock tree report.
c) Timing reports for setup and hold.
d) Power and area report.
Q 14.What is synthesis?
A. It is a process to convert RTL code into design implementation.
Q 15.which metal layer will be used for clock in 7 metal layer design.why?
A. Metal 4 and 5.because the clock nets will consume 30 to 40% of power in the design.So to reduce the IR drop we are using low resistance metal.top 6,7 metal layers for power connection and 5,4 for clock nets.
Q 16.What is antenna effect?
A. Increasing net length can accumulate more changes while manufacturing of the device due to the ionization process.If this net is connected to gate of the MOSFET it can damage dielectric property of gate and causing damage to MOSFET.
Q 17.What is cloning and buffering?
A. Cloning:-it is a method of optimization that decrease the load of heavily loaded cell by replacing the cell.
Buffering:-it is a method of optimization that is used to insert buffer in high fan out nets to decrease the delay.
Q 18.Why NAND gate is preferred than NOR?
A. At transistor level the mobility of electrons is normally three times that of holes compared to nor and NAND gate is faster,less leakage.
Q 19.What is LVS(layout vs schematic)?
A. It is a class of EDA software that determines whether a particular IC layout corresponds to the original schematic of design.
Q 20.What is shielding?
A. Placing ground net in between aggressor and victim nets then voltage discharge on ground net.This will reduce the cross-talk.
Q 21.What is isolation cell?
A. These are special cells required at the interface between blocks which are shutdown and always on.It is necessary to isolate the floating inputs.
Q 22.What is retention flop?
A. These cells are special flops with multiple power supply.When design blocks are switched off for sleep mode data in all flip flop contained desires to retain state for this retention flops must be used.
Q 23.What are the i/p required for CTS?
A. a) Detailed placement database.
b) Target for latency and skew if specified.
c) Buffers or inverters to build the clock tree.
d) NDR rules.
e) Clock tree DRC's.
Q 24.What are the CTS goals?
A. a) Minimize clock skew.
b) Minimize insertion delay.
c) Minimize power dissipation.
Q 25.What are the effects of CTS?
A. a) Clock buffers are added.
b) Congestion may increase.
c) Non-clock cells may have been moved to less ideal location.
d) Can introduces timing and max transition/capacitance violations.
Q 26.What are the different types of cells?
A. Tap cell:- These are used to avoid latch up problem.
End cap cells:- These are placed at the edges to avoid cell damage at the end of the row.
Decap cells:- These are placed between power rail and ground rail to avoid dynamic IR drop.
Filler cells:- These are used to connect the gap between the cells.
ICG cells:- Clock gating cell to avoid dynamic power dissipation.
Pad cells:- To interface with outside devices.i/p to power,clock pins are connected to pad cells and out side also.
JTAG cells:- These are used to check IO connectivity.
Q 27.Why HFNS (high fanout net synthesis)?
A. To balance the load HFNS is performed.too many loads will effects the delay numbers and transition time.Because load is directly proportional to load.By buffering the HFNS the load can be balanced.
Q 28.What is hard macro?
A. The circuit is fixed and we don't know which type of gates using inside.We know only timing information not the functional information.
Q 29.What is soft macro?
A. The circuit is not fixed and we know which type of gates using inside.We know timing information and also functional information.
Q 30.What is the formula for distance between macros?
A. Distance between macros = no.of pins * pitch / total layers.
Q 31.What is CTO(clock tree optimization)?
A. It improves the clock skew and clock insertion delay by applying additional optimization. CTO is performed during clock_opt process.
Q 32.What is the deference between normal buffer and clock buffer?
A. Clock buffer having equal rise and fall time but normal buffer not like that.Clock buffers are usually designed such that an i/p signal with 50% duty cycle produces an o/p with 50% duty cycle.
Q 33.Why should we solve setup violations before CTS and hold violations after CTS?
A. Setup violations depends on data path while hold violations depends on clock path.Before CTS clock path is taken as ideal because we don't have skew and transition numbers of the clock path but this information is sufficient to perform setup analysis.Clock is propagated after CTS that's why hold violations are fixed after CTS.
Q 34.What is global routing?
A. It is done to provide instructions to the detailed router about route every net.It provides the channels for interconnect to be routed.
Q 35.What is detailed routing?
A. It is where we specify the exact location of the wires/inter connects in channels specified by the global routing.Metal layer information of the interconnects are also specified here.
Q 36.What is the use of virtual clock?
A. It will help to reduce the time delay of the overall operation.It is logically not connected to any pin of design and physically does't exist.
Q 37. What is MMMC(multi mode multi corner)?
A. It is a combination of mode and corner that is required for a particular timing check such as setup and hold.
Q 38.What is the difference between hierarchical design and flat design?
A. Hierarchical design has blocks and sub blocks in an hierarchy.Flat design has no sub blocks and it has only leaf cells. Hierarchical design takes more run time and flat design takes less run time.
Q 39.During power analysis if you are facing IR drop problem then how did you avoid?
A. a) Increase power metal layer width.
b) Go for high metal layer.
c) Spread macros or standard cells.
d) Provide more straps.
Q 40.What are the types of routing?
A. a) Global routing.
b) Track assignment.
c) Detailed routing.
d) Search and repair.
Q 41.What is body effect?
A. It is the change in threshold voltage resulting from a voltage difference between the transistor and body.These is caused by body biasing.
Q 42.What is glitch?
A. Glitch is a electric pulse of short duration that is usually the result of fault or design error.
Q 43.What are the benefits of SOI technology?
A. a) Low parasitic capacitance.
b) High peed performance.
c) Reduce short channel effects.
d) No latch up.
e) Low threshold.
Q 44.What are the guidelines for macro placement?
A. Fly-lines,port communication,macros are placed at boundaries,spacing between macros,macro grouping,macro alignment,notches avoiding,orientation,blockages,avoid crisscross placement of macros.
Q 45.What are the sanity checks in pd?
A. a) Check_library.
b) Check_timing.
c) Check_design.
d) Report_constraint.
e) Report_timing.
f) Report_QOR.
Q 46.What is the difference between Halo and Blockage?
A. Halo:- It is the region around the boundary of fixed macros in design in which no other macros or standard cells can be place.If macros moves halo will also move.
Blockage:- It can be specified for any part of the design.If we move the block blockage will not move.
Q 47.Why we apply NDR rules before routing?
A. Some times with default routing it is very hard to avoid cross talk,electromigration.Fixing the cross-talk,electromigration in routing stage is difficult.So we are applying ndr rules(double space,double width) before routing.
Q 48.What are the types of blockages?
A. Hard blockage:- It does't allow inverters,buffers,standard cells.
Soft blockage:- It allows only inverters and buffers and blocks standard cells.
Partial blockage:- It will allow both buffers and standard cell in a percentage value.
Q 49.What is congestion?
A. When the available tracks are less than the required tracks this effect will occur.When the signals are more than the tracks then congestion will occur.
Q 50.How to fix congestion?
A.
Q 1.What is physical design?
A. The physical design is the process of transforming a circuit description into the physical layout which describes position of the cells and routs for the interconnections between them.
Q 2.which design is more complicated 10MHZ or 100MHz?
A. 100mhz. because high frequency means low time period.So it is difficult to handle the violations in low time period.
Q 3.what is floor planing?
A. The floor plan is a process of determining the macro placement,power grid generation and I/O placement.
Q 4.If you have both IR drop and congestion how will you fix it?
A. a) Spreed macros.
b) Spreed standard cells.
c) Increase strap width.
d) Increase no.of straps.
e) Use proper blockage.
Q 5.What are the Tie-high and Tie-low cells?
A. These are used to connect the gate of transistor to either power or ground.It avoid direct connection between power and gate of transistor.
Tie-high:- One terminal is connected to vdd and another terminal is connected to gate of transistor.
Tie-low:- One terminal is connected to vss and another terminal is connected to gate of transistor.
Q 6.What are the checks to be done before cts?
A. a) Placement -completed.
b) Power ground nets -pre-routed.
c) Estimated congestion -acceptable.
d) Estimated timing -acceptable.
e) Estimated max transition/capacitance -no violations.
f) High fan-out nets.
Q 7.What are the power gating cells?
A. The power gating is to avoid static power dissipation.The power gating cells are
a) Power switches.
b) Level sifters.
c) Retention registers.
d) Isolation cells.
e) Power controller.
Q 8.What is HFNS(high fan-out net synthesis)?
A. HFNS is the process of buffering the high fan-out nets to balance the load.
Q 9.Where HFNS is used?
A. Generally at placement stage HFNS is performed.it is also performed at synthesis step using design compiler.
Q 10.What is Electromigration(EM)?
A. When high current density continuously flows through a metal due to the high current the atoms moving with kinetic energy and they transfer the energy to another atoms and increases the temperature due to these the metal will damage.
Q 11.Is zero skew is possible?
A. Practically it is not possible because all the flip flops are not getting the same clock.The skew is exist when the two different clocks are present.Zero skew means all clocks are same practically it is not possible.
Q 12.How to reduce latchup problem?
A. a) Increase spacing between p-well and n-well.
b) Increase well/substrate doping concentration.
c) Use ground rings around device.
Q 13.What are the check list after cts?
A. a) Skew report.
b) Clock tree report.
c) Timing reports for setup and hold.
d) Power and area report.
Q 14.What is synthesis?
A. It is a process to convert RTL code into design implementation.
A. Metal 4 and 5.because the clock nets will consume 30 to 40% of power in the design.So to reduce the IR drop we are using low resistance metal.top 6,7 metal layers for power connection and 5,4 for clock nets.
Q 16.What is antenna effect?
A. Increasing net length can accumulate more changes while manufacturing of the device due to the ionization process.If this net is connected to gate of the MOSFET it can damage dielectric property of gate and causing damage to MOSFET.
Q 17.What is cloning and buffering?
A. Cloning:-it is a method of optimization that decrease the load of heavily loaded cell by replacing the cell.
Buffering:-it is a method of optimization that is used to insert buffer in high fan out nets to decrease the delay.
Q 18.Why NAND gate is preferred than NOR?
A. At transistor level the mobility of electrons is normally three times that of holes compared to nor and NAND gate is faster,less leakage.
Q 19.What is LVS(layout vs schematic)?
A. It is a class of EDA software that determines whether a particular IC layout corresponds to the original schematic of design.
Q 20.What is shielding?
A. Placing ground net in between aggressor and victim nets then voltage discharge on ground net.This will reduce the cross-talk.
Q 21.What is isolation cell?
A. These are special cells required at the interface between blocks which are shutdown and always on.It is necessary to isolate the floating inputs.
Q 22.What is retention flop?
A. These cells are special flops with multiple power supply.When design blocks are switched off for sleep mode data in all flip flop contained desires to retain state for this retention flops must be used.
Q 23.What are the i/p required for CTS?
A. a) Detailed placement database.
b) Target for latency and skew if specified.
c) Buffers or inverters to build the clock tree.
d) NDR rules.
e) Clock tree DRC's.
Q 24.What are the CTS goals?
A. a) Minimize clock skew.
b) Minimize insertion delay.
c) Minimize power dissipation.
Q 25.What are the effects of CTS?
A. a) Clock buffers are added.
b) Congestion may increase.
c) Non-clock cells may have been moved to less ideal location.
d) Can introduces timing and max transition/capacitance violations.
Q 26.What are the different types of cells?
A. Tap cell:- These are used to avoid latch up problem.
End cap cells:- These are placed at the edges to avoid cell damage at the end of the row.
Decap cells:- These are placed between power rail and ground rail to avoid dynamic IR drop.
Filler cells:- These are used to connect the gap between the cells.
ICG cells:- Clock gating cell to avoid dynamic power dissipation.
Pad cells:- To interface with outside devices.i/p to power,clock pins are connected to pad cells and out side also.
JTAG cells:- These are used to check IO connectivity.
Q 27.Why HFNS (high fanout net synthesis)?
A. To balance the load HFNS is performed.too many loads will effects the delay numbers and transition time.Because load is directly proportional to load.By buffering the HFNS the load can be balanced.
Q 28.What is hard macro?
A. The circuit is fixed and we don't know which type of gates using inside.We know only timing information not the functional information.
Q 29.What is soft macro?
A. The circuit is not fixed and we know which type of gates using inside.We know timing information and also functional information.
Q 30.What is the formula for distance between macros?
A. Distance between macros = no.of pins * pitch / total layers.
Q 31.What is CTO(clock tree optimization)?
A. It improves the clock skew and clock insertion delay by applying additional optimization. CTO is performed during clock_opt process.
Q 32.What is the deference between normal buffer and clock buffer?
A. Clock buffer having equal rise and fall time but normal buffer not like that.Clock buffers are usually designed such that an i/p signal with 50% duty cycle produces an o/p with 50% duty cycle.
Q 33.Why should we solve setup violations before CTS and hold violations after CTS?
A. Setup violations depends on data path while hold violations depends on clock path.Before CTS clock path is taken as ideal because we don't have skew and transition numbers of the clock path but this information is sufficient to perform setup analysis.Clock is propagated after CTS that's why hold violations are fixed after CTS.
Q 34.What is global routing?
A. It is done to provide instructions to the detailed router about route every net.It provides the channels for interconnect to be routed.
Q 35.What is detailed routing?
A. It is where we specify the exact location of the wires/inter connects in channels specified by the global routing.Metal layer information of the interconnects are also specified here.
Q 36.What is the use of virtual clock?
A. It will help to reduce the time delay of the overall operation.It is logically not connected to any pin of design and physically does't exist.
Q 37. What is MMMC(multi mode multi corner)?
A. It is a combination of mode and corner that is required for a particular timing check such as setup and hold.
Q 38.What is the difference between hierarchical design and flat design?
A. Hierarchical design has blocks and sub blocks in an hierarchy.Flat design has no sub blocks and it has only leaf cells. Hierarchical design takes more run time and flat design takes less run time.
Q 39.During power analysis if you are facing IR drop problem then how did you avoid?
A. a) Increase power metal layer width.
b) Go for high metal layer.
c) Spread macros or standard cells.
d) Provide more straps.
Q 40.What are the types of routing?
A. a) Global routing.
b) Track assignment.
c) Detailed routing.
d) Search and repair.
Q 41.What is body effect?
A. It is the change in threshold voltage resulting from a voltage difference between the transistor and body.These is caused by body biasing.
Q 42.What is glitch?
A. Glitch is a electric pulse of short duration that is usually the result of fault or design error.
Q 43.What are the benefits of SOI technology?
A. a) Low parasitic capacitance.
b) High peed performance.
c) Reduce short channel effects.
d) No latch up.
e) Low threshold.
Q 44.What are the guidelines for macro placement?
A. Fly-lines,port communication,macros are placed at boundaries,spacing between macros,macro grouping,macro alignment,notches avoiding,orientation,blockages,avoid crisscross placement of macros.
Q 45.What are the sanity checks in pd?
A. a) Check_library.
b) Check_timing.
c) Check_design.
d) Report_constraint.
e) Report_timing.
f) Report_QOR.
Q 46.What is the difference between Halo and Blockage?
A. Halo:- It is the region around the boundary of fixed macros in design in which no other macros or standard cells can be place.If macros moves halo will also move.
Blockage:- It can be specified for any part of the design.If we move the block blockage will not move.
Q 47.Why we apply NDR rules before routing?
A. Some times with default routing it is very hard to avoid cross talk,electromigration.Fixing the cross-talk,electromigration in routing stage is difficult.So we are applying ndr rules(double space,double width) before routing.
Q 48.What are the types of blockages?
A. Hard blockage:- It does't allow inverters,buffers,standard cells.
Soft blockage:- It allows only inverters and buffers and blocks standard cells.
Partial blockage:- It will allow both buffers and standard cell in a percentage value.
Q 49.What is congestion?
A. When the available tracks are less than the required tracks this effect will occur.When the signals are more than the tracks then congestion will occur.
Q 50.How to fix congestion?
A.
- Congestion driven placement.
- Adjust cell density in congested area(high cell density cause congestion).
- Use proper blockage.
- Modify the floor plan design.
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