PD interview questions and answers - part 3

by kamalnadh

1. What are the types of operating modes?
A. a) Test mode.
     b) Scan mode.
     c) Reset mode.
     d) Functional mode.

2. What is test mode and functional mode?
A. Test mode will detects manufacturing faults after fabrication and functional mode will detects faults at logic.

3.  What is Test clock?
A. If there is a separate clock for scan mode then that clock is known as Test clock.

4. What are the types of timing modes?
A. a) Single mode :- setup and hold check with a single library.
     b) Best case/Worst case mode :- setup with worst case mode and hold with best case mode.
     c) On chip variation mode :- setup and hold check with best case mode(lib1) and worst case mode(lib2)

5. How can you know your netlist is good or bad?
A. If given netlist has buffering on clock and reset then it is not a good netlist.

6. What is FIRE ICE?
A. Fast Interconnect Resistance Extractor Interconnect Capacitance Extractor(FIRE ICE) is a tool for RC extraction.

7. What is Tap current?
A. It is the current drawn by the each and every transistor or standard cell.Based on width of standard cell we can calculate the current value this current is known as tap current.

8. What is the manufacturing grid value?
A. It is the minimum value anything which is less than manufacturing grid value can't be read.

9. Why we use layer map file?
A. It is used for interaction(mapping) between the QRC tech file and tech lef.QRC tech file and lef file contains different names for same metals to over come this problem we use layer map file.

10. What is delay cell?
A. To fix hold tool will add cells in data path these cells are known as delay cells.It just produce output same as input with some delay.

11. What is timing window?
A. Difference between early arrival time and late arrival time for each and every net is known as timing window.

12. Is all the glitches are harmful?
A. All the glitches are not harmful.The glitches whose amplitude is more than VIL(low input voltage) then it will cause problem.

13. What is LEC check?
A. Optimized netlist must checked with final RTL netlist whether  they are logically matched or not.

14. What are the types of wire load models?
A. a) Zero wire load model.
     b) Standard wire load model.
     c) Customized wire load model.
     d) Auto wire load model.

15. Why we don't use HVT cells in lower technologies?
A. HVT cells responds to temperature inversion more effectively.so we don't use HVT cells.

16. What is physical knowledgeable synthesis?
A. After completion of floor plan and placement giving this information to logic synthesis is known as  physical knowledgeable synthesis.

17. What is Steiner?
A. Routing the design with shortest path instead of H-V-H-V(horizontal vertical horizontal vertical) function(this is illegal ).

18. What is top-down methodology?
A. In this we need to synthesis entire RTL code of chip in a single slot.

19. What is black box?
A. In bottom-up approach if A&C block timing is closed but we are still working on B block then make B block as black box.

20. What is the tool used for Rc extraction?
A. Cadence :- QRC.
     Synopsys :- Star RC.

21. What is the tool used for Signoff?
A. Cadence :- ETS.
      Synopsys : Prime Time.

22. What is the tool used for Physical verification?
A. Cadence :- Assura.
     Synopsys :- Hercules.

23. What is the tool used for Logical synthesis?
A. Cadence :- RTL compiler.
     Synopsys :- Design compiler.

24. What is the tool used for Physical synthesis?
A. Cadence :- Encounter gps,pks.
     Synopsys :- Physical compiler.

25. What is the tool used for PNR?
A. Cadence :- SOC encounter.
     Synopsys :- IC compiler.

PD interview questions and answers -part 2

by kamalnadh

Q 1.What are the types in physical verification?
 A. LVS (layout vs schematic).
      DRC (design rule constrain check).
      ERC (electric rule check).
      LEC (logical equivalence check).

Q 2.How to fix setup and hold violations at a time?
A. It is not possible to fix both at a time because if we increase the delay in data path it's good for hold and bad for setup.But there is only one way to fix it.

• Buffer the data path for hold fix.
• Slow the clock frequency for setup fix (this is not a valid fix,but we don't have other option).

Q 3.How can you avoid cross-talk?
A. a) Increase the spacing between the aggressor and victim nets.
     b) Shielding.
     c) Maintain the stable supply.
     d) Increase the drive strength of cell.
     e) Layer jumping.
     f) Victim net width increasing then resistance decreases.
     g) Guard ring.
     h) Cell sizing (up sizing).


Q 4.What is cross-talk?

A. It is the undesirable electric interaction between two or more physical adjust nets due to the capacitance cross coupling.When two nets are in parallel the electric field of one net is effects the other net which is nearer to it.This called cross-talk effect. 

Q 5.What is scan chain reordering?

A. It is the process of re connecting the scan chains in the design to optimize for routing by reordering the scan chain connection which improves timing and congestion.

Q 6.What is the concept of rows in the floor plan?
A. The std-cells in the design are placed in rows.All rows have equal height and spacing.The width of the row can vary.The std-cell in the row get the power and ground connection from vdd and vss rails.Sometimes technology allows the rows to be flip.So they can share the power  and ground rails in vdd-vss-vdd patron.


Q 7.What are the advantages of NDR's?
A. a) By applying the double width we can avoid the EM.
     b) By applying double spacing we can avoid the cross-talk.
     c) Help's to avoid congestion at lower metal layer.
     d) Help's pin accessibility of std-cells .

Q 8.What is temperature inversion?
 A. At higher CMOS technologies cell delay increases when temperature increases.But when you are in lower technologies i.e below 65nm cell delay has inversely proportional to temperature.

Q 9.In reg to reg path if you have setup problem where will you insert buffer?
A. We can insert buffer near to launch flop which decreases the transition time.Hence decreasing the wire delay therefore overall delay will decrease.When arrival time will decrease setup violations will reduce(required time-arrival time).

Q 10.What is partitioning?
A. It is the process of dividing the chip into small blocks this is done mainly to separate different functional blocks and also make placement.routing easier.

Q 11.How can you reduce dynamic power?
A. a) Reduce power supply voltage.
     b) Reduce voltage swing in all nodes.
     c) Reduce the switching probability (transition factor).
     d) Reduce load capacitance.

Q 12. Why double via insertion?
A. To reduce the yield loss due to via failures,double via's are inserted traditionally double via's where inserted in post route and then modify the routing to fix any DRC's.

Q 13.What is metal fill insertion?
A. At the time of etching they use some type of chemicals due to that chemical metal loss will be more for that reaction we are inserting the metal fills.

Q 14.What is metal slotting?
A. It is the Technic for avoiding the problems like metal lift off and metal erosion.

Q 15.What are the power dissipation components?
A. Dynamic power consumption:- Occurs when signals which go through the CMOS circuit change there logic state by charging discharging of o/p node capacitor.
static (leakage power consumption):- It is the power consumed by the sub threshold currents and by reverse biased diodes in a CMOS transistor.
short circuit power consumption:- It occurs during switching on both the NMOS and PMOS transistors in the circuit and they conduct simultaneously for a short amount of time.

Q 16.What is dishing effect?
A. It is defined as the difference between the height of the oxide in the spaces and that of the metal in the trenches.It is caused by CMP.It may reduced by some dummy fill Technics effectively.

Q 17.What is CMP (chemical mechanical polishing)?
A. It is the process of smoothing surface with the combination of chemical and mechanical forces.It is used in IC fabrication to get a high level of polarization.

Q 18.What is the use of placement blockage?
A. a) Defines std-cell and macro area.
     b) Reserve channels for buffer insertion.
     c) Prevent cells from being placed at or near macros.
     d) Prevent congestion near macros.

Q 19.What are the types of global routing?
A. a) Time driven global routing.
     b) Cross-talk driven global routing.
     c) Incremental global routing.

Q 20.What are the violations solved in LVS?
A. a) Shorts.
     b) Opens.
     c) Missing text layers.
     d) Missing lib in GDS.
     e) Missing soft layers.

Q 21.What is the clock latency?
A.It is the delay between the clock source and clock pin.It is two types.Clock source latency and clock network latency.The time taken from clock source to definition pin is the clock source latency and from the clock definition pin to clock pin of the flip flop 2 is the clock network latency.

Q 22.How to fix setup and hold violations?
A. Setup:-

• Reduce the amount of buffers in the path.
• Replace buffers with 2 inverters.
• Replace HVT cells with LVT cells.
• Increase the drive size/strength.
• Insert repeaters.
• Adjust cell position in layout.

     Hold:-

• By adding delay in data path.
• Decrease the drive strength in data path.

Q 23.What are the inputs of floor plan?

A.

• .v
• .lib and .lef
• .sdc
•  tlu+ file
•  Physical partitioning information of design.
•  Floor plan parameters like height,width,aspect ratio,utilization.
•  Pin/pad position.

Q 24.What are the outputs of floor plan?
A. 

• Die/block area.
•  I/O pad placed.
•  Macro placed.
•  Power grid design.
•  Power pre routing.
•  Std-cell placement area.

Q 25.What is keep-out margin?
A. It is the region around the boundary of fixed macros in design in which no other macros or standard cells not allows.It allows only buffers and inverters in it's area.

Q 26.How will you synthesize clock tree?
A.a) Single clock-normal synthesis and optimization.
    b) Multiple clocks-synthesis each clock separately.
    c) Multiple clocks with domine crossing synthesis each clock                separately and balance the skew.

Q 27.What is IR drop?
A. Each metal layer has a resistance value.When the current flows through the metal the resistance consumes some current.This is the IR drop.If the resistance is more the drop also more.

Q 28.how to reduce power dissipation using HVT and LVT in the design?
A.If we have positive slack use HVT cells in the path and use LVT cells in the path when we have negative slack.HVT cells have large delay and less leakage power. LVT cells have less delay and      more leakage power.To meet the timing use LVT cells and to reduce the leakage power use HVT cells.


Q 29.What is wire load model (WLM)?
A. It is an estimation of delay based on area and fan-out.The delay depend on..
     Resistance.
     Capacitance.
     Area of the nets.

Q 30.What is signal integrity?
A. It is the ability of an electric signal to carry information reliably and to resist the effects (cross-talk, EM) of high frequency electromagnetic interface from near by signals.

Q 31.Doe's cross-talk always cause violations?
A.Yes it is because cross-talk adds or subtracts energy to the signal which cause setup or hold violations.

Q 32.How a positive or negative edge triggered flip flop will effect the setup and hold violations?
A. Positive edge triggered flip flop will favour to setup (setup violations will reduce).Negative edge triggered flip flop will favour to hold (hold violations will reduce).

Q 33.What are the i/p's and o/p's of power planing?
A. i/p's:-

• Data base with valid floor plan.
• Power rings and power straps width.
• Spacing between vdd and vss straps.

     o/p:-

• Design with power structure.

Q 34.What are the i/p's and o/p's of placement?
A. I/P's:-

• Netlist.
• Mapped and floor planed design.
• Logical and physical lib.
• Design constraints.

    O/P 's:-

• Physical layout information.
• Cell placement location.
• Physical layout,timing and technical information of lib.

Q 35.If we increase the fan-out of the cell how it will effects delay?
A. Fan-out lead to increased capacitive load on the driving gate.Therefore longer propagation delay.

Q 36.What is multi driven nets?
A. It can be created in RTL by introducing drivers of same or different signal strengths.However during a net with multiple signals are not considered as a good practice.This could lead to failure in a post silicon verification as the driver strength can potentially get heavily altered during manufacturing defects.Many EDA tools don't allow multi driven nets in the design and the designers are expected to remove all multi driven nets from the design.

Q 37.What is magnetic placement?
A. To improve the timing for the design or to improve the congestion for a complex floor plan we can use magnetic placement to specify fixed objects as magnets and icc moves their connected standard cells close to them.For the best results perform the magnetic placement before standard cells are placed.

Q 38.What is lookup table?
A.The table is drawn by using input transition and output load values.It is used to calculate the cell delay.

Q 39.What does we do for low power design?
A. We apply low power techniques

• Clock gating.
• Multi voltage design.
• Power gating.
• Multiple vt libraries.

Q 40.What are the types of checks done in prime time?
A. a) Timing (setup,hold,transition).
     b) Design constraints.
     c) Nets.
     d) Noise.
     e) Clock skew.

Q 41.What analysis we do during floor plan?
A.a) Overlapping of macros.
     b) Allowable IR drop.
     c) Global route congestion.
     d) Physical information of the design.

Q 42. What are the different types of delay models?
A. a) WLM (wire load model)
     b) NLDM ( non linear delay model)
     c) CCS (composite current source)

Q 43.Where placement blockage is created?
A. At floor plan stage it acts like guidelines for placement of standard cells.In CTS stage in order to balance the skew more  no.of buffers and inverters are added and blockages are used to reserve space for buffer and inverter.

Q 44.Why we apply NDR's in placement?
A. Applying NDR's in placement because of avoiding congestion and timing problem.These problems are difficult to fix at routing.These are special rules like double spacing and double width.

Q 45.What is mesh?
A. The horizontal and vertical power straps in the design are called mesh.

Q 46.Why I/O cells are placed in the design?
A. The i/o cells are the one which interact in between the blocks outside of the chip to internal blocks of the chip.In floor plan stage i/o cells are placed in between core and die.These are responsible for providing voltage to the cell in the core.

Q 47.What are the complex cells in the floor plan?
A.These are the cells which are made of group of std-cells based on functionality requirement.This cells height is grater than the std-cells and lesser than the macros.

Q 48.How to fix Electromigration (EM)?
A. a) Down size the driver.
     b) Increase the metal width.
     c) Add more vias.
     d) Spread cells.

Q 49.What is etching?
A.It is used in micro-fabrication to chemically remove layers from the surface of the wafer during manufacturing.

Q 50.What is SOI technology?
A.It refers to use of layered silicon insulator.It reduces leakage current and lower power consumption.

Q 51.What is aggressor and victim?
A.these two terms will come in cross-talk concept.
    Aggressor:- A net which create the effect on nearer net(victim).
    victim:- A net which receives the effect from nearer net(aggressor).

Q 52. What is Mealy and Moore?
A. Mealy:- The outputs are depends on input and present state.
     Moore:- The outputs are depends on only present state.


     

  

Physical design flow

by kamalnadh


PD flow:-

Physical design:-  It is the process of transforming a circuit description into physical layout.which describes the position of cells and routes for the interconnection between them.the physical design process stages are listed below.

Import design:-

           It is the first stage in physical design.In synthesis process the RTL code is converted into netlist.In this import design stage all input files are read by the tool.By using this information the design process will starts.

Floorplan:-
            The floorplan is the process of determining the macro placement,power grid generation and i/o placement.It is the process of placing blocks/macros in the chip/core area there by determining routing areas between them.It determines the size of the die and creates wire tracks for placement of standard cells.It creates power straps and specifies pg connection.It also determine the i/o ,pin/pad placement information.

                      

Placement:-
          Placement is the process of automatically assigning correct position to standard cells on the chip with no overlapping.By global placement outside of standard cells will placed inside roughly.By the detailed placement the standard cells will place in site rows(legalize placement).In placement stage we check the congestion value by GRC map.

(Note:- For just understanding purpose standard cell size was increased.in practical standard cell and rows are too small compare to macros.Count of std cells also high.ex:-50k)

CTS(clock tree synthesis):-
               In this stage we built the clock tree by using inverters and buffers.In the chip clock signal is essential to the flip flops,to give the clock signal from clock source we built the clock tree.It is the process of balancing the clock skew and minimizing insertion delay in order to meet timing and power.

Routing:-

               Before the routing stage the connection between the macros,standard cells,clock,i/o port are logical connections.In this stage we connect all the cells physically with the metal straps.Routing is divided as two parts 1)global routing 2)detailed routing.The global routing will tell for which signal which metal layer is used.Before the detailed routing all are the logical connections.In detailed routing the physical connections are done.

Signoff:-
              After the routing the physical layout of chip is completed.In signoff stage all the tests are done to check the quality and performance of the layout before tapeout.

Placement

by kamalnadh

                              Placement
                            
                   Placement is the process of automatically assigning correct position to standard cells on the chip with no overlapping. By global placement outside of standard cells will placed inside roughly.By the detailed placement the standard cells will place in site rows(legalize placement).In placement stage we check the congestion value by GRC map.

Inputs of placement:-

•  Floorplan design.
•  Netlist.
•  Design constraints.
•  Logical library(.lib),physical library(.lef).

Before discussing about placement let see few definitions in placement.

Blockage:- Blocking a specific are to prevent placing of cells.

Hard blockage:- It does't allow inverters,buffers,standard cells.

Soft blockage:- It allows only inverters and buffers and blocks standard cells.

Partial blockage:- It will allow both buffers and standard cell in a percentage value.

Congestion:- when the available tracks are less than the required tracks this effect will occur.When the signals are more than the tracks then congestion will occur.

HFNS (high fan-out net synthesis ):- HFNS is the process of buffering the high fan-out nets to balance the load.

Scan chain:- It is used in design for testing.It makes testing easier by setting a group of Flip-flops connecting serially.

Goals of placement:-

• Minimum congestion.
• Minimum timing DRC's.
• Timing power and area optimization.
• Minimum cell density,pin density and congestion hotspots.

Process in the placement:-

• Course placement:- In floor plan stage we place only macros inside the chi.In placement we place standard cells inside the core.by the course placement outside of standard cells will place inside roughly.

       

(Note:- for just understanding purpose standard cell size was increased.in practical standard cell and rows are too small compare to macros)

• Legalize placement:- By the course placement standard cells overlaps on the rows.To fix this we are doing legalize placement.by this legalize placement all the standard cells are fixed in rows

        

(Note:- for just understanding purpose standard cell size was increased.in practical standard cell and rows are too small compare to macros)

• Congestion analysis:- when available tracks are less then the required tracks then congestion will occur.The congestion range can be estimated by GRC map.

       Congestion reduction techniques:-

       a) Congestion driven placement.

       b) Adjust cell density in congested area(high cell density cause            congestion).

       c) Use proper blockage.

       d) Modify the floor plan design.

• Blockage:- To reduce the congestion we have to use proper blockage.There are three types of blockages hard blockage,soft blockage and partial blockage.By the blockage cells will not overlap.Macro padding and cell padding are the placement blockages.In macro padding the area around the macro is blocked so no std cells will place near to macro.

• HFNS (high fan-out net synthesis):- Fan-out is the maximum number of inputs that a single output of logic gate.To balance the load HFNS is performed.Too many loads will effects the delay numbers and transition time.because load is directly proportional to load.by buffering the HFN the load can be balanced. 

• placement optimization:- It can be done by different options like area recovery,DFT,power,congestion and timing.By using power option we can reduce the static and dynamic power consumpion.By using area recovery we can reduce the cells,power and timing.By scan chain reordering(DFT) we can reduce the routing length. 

Scan chain reordering:- 
                 Scan chain  is used in design for testing.It makes testing easier by setting a group of Flip-flops connecting serially.but in placement stage all the flip-flops are not placed serially (ex:- FF 1 is placed at one corner and FF 2 is placed another corner) but scan chain will connect serially like FF 1 to FF 2 to FF 3.this will leads to increase in routing length and crisscross connection then congestion will increase.In order to decrease this crisscross connection and routing length we are doing scan chain reordering.In this the FF 1 will connect to nearer flip-flop.which will reduce crisscross connections.By the scan chain reordering congestion will reduce but some time it will increase hold time problem in the chain.To over come this buffers inserted in scan path.

Fig 1

Fig 2

Fig 1 shows before scan chain reordering flip-flops are connected serially like FF1-FF2-FF3-FF4. This will increase the routing length and crisscross connections (congestion).
Fig2 shows after scan chain reordering flip-flops are connected nearer by them like FF1-FF3-FF2-FF4. This will decrease the routing length and congestion also decreases.

Power optimization:-
      Now a days most of devices targeted to consume less power because consumers also expecting less power power consumption devices.We have two types of power dissipation.

Static power dissipation:- It is also called leakage power.It can be reduced by replacing LVT cells with HVT cells in a percentage.Because HVT cells have less leakage power.Some architectures will use power gating to reduce static power.

Dynamic power dissipation:- Dynamic power dissipation is due to load and high switching activities.These power can be reduced by reducing the load capacitance,cell sizing,sharing the load.


Outputs of placement:-

• Timing information.
• Congestion report.
• Physical layout information.
• Cell placement location.

CTS

by kamalnadh

                                   CTS
        In this stage we built the clock tree by using inverters and buffers.In the chip clock signal is essential to the flip flops,to give the clock signal from clock source we built the clock tree.It is the process of balancing the clock skew and minimizing insertion delay in order to meet timing and power.

 Before discussing about CTS let see few definitions in CTS.

Aggressor:- A net which creates the effect on nearer net(victim).

Victim:- A net which receives the effect from nearer net(aggressor).

Shielding:- Placing ground net in between aggressor and victim net then voltage discharge on ground net.This will reduce cross-talk.

Cross-talk:- It is the undesirable electric interaction between two or more physical adjust nets due to the capacitance cross coupling.

CTO(clock tree optimization):- It improves the clock skew and clock insertion delay by applying additional optimization. CTO is performed during clock_opt process.

Inputs required for cts:-

• Detailed placement database.
• Target for latency and skew if specified.
• Buffers or inverters for building the clock tree.
• Clock tree DRC's.

Checks before cts:-

• Completed placement.
• Power ground nets - pre routed.
• Acceptable congestion.
• Estimated timing.
• HFNS.

Process:-

      It is a process of inserting buffers and inverters along with the clock path to balance the delay to all clock inputs. Before CTS we treat clock as ideal.If we did't built the clock the skew and insertion delay will increases.This will effects the chip performance.To overcome this we are constructing the clock tree by using inverters and buffers.Below fig shows the structure of before CTS and after CTS.

    Fig:-Before CTS

Fig:-After CTS

Clock tree optimization (CTO):-

It improves the clock skew and clock insertion delay by applying additional optimization. CTO is performed during clock_opt process.The CTO techniques are listed below

Delay insertion:- It will improve hold time.

Buffering:- It will improve setup time.

Buffer relocation:- Reduce skew and insertion delay.

Level adjustment:- Adjust a level of clock pins to a higher or lower

Gate sizing:- It may decrease the delay.

To fix max transition add buffers and to fix max capacitance decrease the net length,cloning.

NDR's:-
Non default rules are applied to reduce the cross-talk and electromigration.NDR's like double spacing,double width shielding.
By applying double spacing cross-talk will reduce.
By applying double width we can avoid electromigration.

Cross-talk:- 

          It is the undesirable electric interaction between two or more physical adjust nets due to the capacitance cross coupling.when two nets are in parallel the electric field of one net is effects the other net which is nearer to it.This called cross-talk effect.

The above fig explain the cross-talk effect.There are two nets running parallel and spacing between the nets are less so capacitance is more.The input of aggressor net inverter is falling signal and the output is raising edge.The input of victim net inverter is raising signal and the output is falling signal.When the rising edge signal is entering into the aggressor net 2nd inverter the charge will stores in the capacitance due to electrical interference at the same time the charge stored in the capacitance will discharge on falling signal of victim net 2nd inverter input.Due to this the falling signal will effect.Here 1st net is creating the effect so that is aggressor and second net receiving effect so that is victim.

Cross-talk reducing techniques:-
a) Increase the spacing between the aggressor and victim nets.
b) Shielding.
c) Maintain the stable supply.
d) Increase the drive strength of cell.
e) Layer jumping.
f) Victim net width increasing then resistance decreases.
g) Guard ring.
h) Cell sizing (up sizing).

CTS exceptions:-

Stop pins:- These are the end point of clock tree and used in calculation and optimization of DRC and clock tree timing(skew,insertion delay).

Float pins:- It's like stop pins with additional delay.

Exclude pins:- It is used only in calculation and optimization of DRC's.It not target skew and insertion delay.


Checklist after cts:-

• Skew report.
• Clock tree report.
• Timing report for setup and hold.
• Power and area report.

CTS goals:-

• Balancing the skew.
• Minimizing insertion delay.
• Minimizing power dissipation.
• Meet the logical DRC's.

Routing

by kamalnadh

Routing:-
               Before the routing stage the connection between the macros,standard cells,clock,i/o port are logical connections.In this stage we connect all the cells physically with the metal straps.The routing done in different steps.

Steps in routing:-

   1.Global routing.

   2.Track assignment.

   3.Detailed routing.

   4.Search and repair.

Global routing:- It is done to provide instructions to detailed routing about where to route every net.It  provides the logical connections to all cells.First the design is divided into small boxes which are called Gcell. Each Gcell have the horizontal and vertical routing resources.It's aim is to reduce the total interconnect length and minimize the critical path delay.By using global routing we can analyse congestion.

Track assignment:- It assigns each net to a specific track and lays down the actual metal tracks.

Detailed routing:-   Before detailed routing the connections are logical.In this stage all the cells are physically connected.In this we specifies the wire/interconnection in the channels specified by the global routing.Metal layer information of the interconnections are also specified here.The violations that are created in track assignment are fixed in this stage.It does't route entire chip at a time.By dividing the chip into small boxes(G cells) it will do routing. DRC's are fixed in detailed routing.

Search and repair:- It fixes the remaining DRC violations  through multiple loops using progressive layer Sbox sizes.

Goals of routing:-

• Minimize the total wire length.
• Minimizing the congestion hotspots.
• Reducing the cross-talk.
• Minimizing no.of via's.
• Meeting the timing DRC's.

PD interview questions and answers -part 1

by kamalnadh

Q 1.What is physical design?
A. The physical design is the process of transforming a circuit description into the physical layout which describes position of the cells and routs for the interconnections between them.

Q 2.which design is more complicated 10MHZ or 100MHz?
A. 100mhz. because high frequency means low time period.So it is difficult to handle the violations in low time period.

Q 3.what is floor planing?
A. The floor plan is a process of determining the macro placement,power grid generation and I/O placement.

Q 4.If you have both IR drop and congestion how will you fix it?
A.  a) Spreed macros.
      b) Spreed standard cells.
      c) Increase strap width.
      d) Increase no.of straps.
      e) Use proper blockage.

Q 5.What are the Tie-high and Tie-low cells?
A. These are used to connect the gate of transistor to either power or ground.It avoid direct connection between power and gate of transistor.
Tie-high:- One terminal is connected to vdd and another terminal is connected to gate of transistor.
Tie-low:- One terminal is connected to vss and another terminal is connected to gate of transistor.

Q 6.What are the checks to be done before cts?
A. a) Placement -completed.
     b) Power ground nets -pre-routed.
     c) Estimated congestion -acceptable.
     d) Estimated timing -acceptable.
     e) Estimated max transition/capacitance -no violations.
     f) High fan-out nets.

Q 7.What are the power gating cells?
A. The power gating is to avoid static power dissipation.The power gating cells are
     a) Power switches.
     b) Level sifters.
     c) Retention registers.
     d) Isolation cells.
     e) Power controller.

Q 8.What is HFNS(high fan-out net synthesis)?
A. HFNS is the process of buffering the high fan-out nets to balance the load.

Q 9.Where HFNS is used?
A. Generally at placement stage HFNS is performed.it is also performed at synthesis step using design compiler.

Q 10.What is Electromigration(EM)?
A. When high current density continuously flows through a metal due to the high current the atoms moving with kinetic energy and they transfer the energy to another atoms and increases the temperature due to these the metal will damage.

Q 11.Is zero skew is possible?
A. Practically it is not possible because all the flip flops are not getting the same clock.The skew is exist when the two different clocks are present.Zero skew means all clocks are same practically it is not possible.

Q 12.How to reduce latchup problem?
A. a) Increase spacing between p-well and n-well.
     b) Increase well/substrate doping concentration.
     c) Use ground rings around device. 

Q 13.What are the check list after cts?
A. a) Skew report.
     b) Clock tree report.
     c) Timing reports for setup and hold.
     d) Power and area report.

Q 14.What is synthesis?
A. It is a process to convert RTL code into design implementation.

Q 15.which metal layer will be used for clock in 7 metal layer design.why?
A. Metal 4 and 5.because the clock nets will consume 30 to 40% of power in the design.So to reduce the IR drop we are using low resistance metal.top 6,7 metal layers for power connection and 5,4 for clock nets.

Q 16.What is antenna effect?
A. Increasing net length can accumulate more changes while manufacturing of the device due to the ionization process.If this net is connected to gate of the MOSFET  it can damage dielectric property of gate and causing damage to MOSFET.

Q 17.What is cloning and buffering?
A. Cloning:-it is a method of optimization that decrease the load of  heavily loaded cell by replacing the cell.
Buffering:-it is a method of optimization that is used to insert buffer in high fan out nets to decrease the delay.

Q 18.Why NAND gate is preferred than NOR?
A. At transistor level the mobility of electrons is normally three times that of holes compared to nor and NAND gate is faster,less leakage. 

 Q 19.What is LVS(layout vs schematic)?
A. It is a class of EDA software that determines whether a particular IC layout corresponds to the original schematic of design.

Q 20.What is shielding?
A. Placing ground net in between aggressor and victim nets then voltage discharge on ground net.This will reduce the cross-talk.

Q 21.What is isolation cell?
A. These are special cells required at the interface between blocks which are shutdown and always on.It is necessary to isolate the floating inputs.

Q 22.What is retention flop?
A. These cells are special flops with multiple power supply.When design blocks are switched off for sleep mode data in all flip flop contained desires to retain state for this retention flops must be used.

Q 23.What are the i/p required for CTS?
A. a) Detailed placement database.
     b) Target for latency and skew if specified.
     c) Buffers or inverters to build the clock tree.
     d) NDR rules.
     e) Clock tree DRC's.

Q 24.What are the CTS goals?
A. a) Minimize clock skew.
     b) Minimize insertion delay.
     c) Minimize power dissipation.

Q 25.What are the effects of CTS?
A. a) Clock buffers are added.
     b) Congestion may increase.
     c) Non-clock cells may have been moved to less ideal location.
     d) Can introduces timing and max transition/capacitance violations.

Q 26.What are the different types of cells?
A. Tap cell:- These are used to avoid latch up problem.
End cap cells:- These are placed at the edges to avoid cell damage at the end of the row.
Decap cells:- These are placed between power rail and ground rail to avoid dynamic IR drop.
Filler cells:- These are used to connect the gap between the cells.
ICG cells:- Clock gating cell to avoid dynamic power dissipation.  
Pad cells:- To interface with outside devices.i/p to power,clock pins are connected to pad cells and out side also.
JTAG cells:- These are used to check IO connectivity. 

Q 27.Why HFNS (high fanout net synthesis)?
A. To balance the load HFNS is performed.too many loads will effects the delay numbers and transition time.Because load is directly proportional to load.By buffering the HFNS the load can be balanced. 

Q 28.What is hard macro?
A. The circuit is fixed and we don't know which type of gates using inside.We know only timing information not the functional information.

Q 29.What is soft macro?
A. The circuit is not fixed and we know which type of gates using inside.We know timing information and also functional information.

Q 30.What is the formula for distance between macros?
A. Distance between macros = no.of pins * pitch / total layers.

Q 31.What is CTO(clock tree optimization)?
A. It improves the clock skew and clock insertion delay by applying additional optimization. CTO is performed during clock_opt process.

Q 32.What is the deference between normal buffer and clock buffer?
A. Clock buffer having equal rise and fall time but normal buffer not like that.Clock buffers are usually designed such that an i/p signal with 50% duty cycle produces an o/p with 50% duty cycle.

Q 33.Why should we solve setup violations before CTS and hold violations after CTS?
A. Setup violations depends on data path while hold violations depends on clock path.Before CTS clock path is taken as ideal because we don't have skew and transition numbers of the clock path but this information is sufficient to perform setup analysis.Clock is propagated after CTS that's why hold violations are fixed after CTS.

Q 34.What is global routing?
A. It is done to provide instructions to the detailed router about route every net.It provides the channels for interconnect to be routed.

Q 35.What is detailed routing?
A. It is where we specify the exact location of the wires/inter connects in channels specified by the global routing.Metal layer information of the interconnects are also specified here.

Q 36.What is the use of virtual clock?
A. It will help to reduce the time delay of the overall operation.It is logically not connected to any pin of design and physically does't exist.

Q 37. What is MMMC(multi mode multi corner)?
A. It is a combination of mode and corner that is required for a particular timing check such as setup and hold.
  
Q 38.What is the difference between hierarchical design and flat design?
A. Hierarchical design has blocks and sub blocks in an hierarchy.Flat design has no sub blocks and it has only leaf cells. Hierarchical design takes more run time and flat design takes less run time. 

Q 39.During power analysis if you are facing IR drop problem then how did you avoid?
A. a) Increase power metal layer width.
     b) Go for high metal layer.
     c) Spread macros or standard cells.
     d) Provide more straps.

Q 40.What are the types of routing?
A. a) Global routing.
     b) Track assignment.
     c) Detailed routing.
     d) Search and repair.

Q 41.What is body effect?
A. It is the change in threshold voltage resulting from a voltage difference between the transistor and body.These is caused by body biasing.

Q 42.What is glitch?
A. Glitch is a electric pulse of short duration that is usually the result of fault or design error.

Q 43.What are the benefits of SOI technology?
A. a) Low parasitic capacitance.
     b) High peed performance.
     c) Reduce short channel effects.
     d) No latch up.
     e) Low threshold.

Q 44.What are the guidelines for macro placement?
A. Fly-lines,port communication,macros are placed at boundaries,spacing between macros,macro grouping,macro alignment,notches avoiding,orientation,blockages,avoid crisscross placement of macros.

Q 45.What are the sanity checks in pd?
A. a) Check_library.
     b) Check_timing.
     c) Check_design.
     d) Report_constraint.
     e) Report_timing.
     f) Report_QOR.

Q 46.What is the difference between Halo and Blockage?
A. Halo:- It is the region around the boundary of fixed macros in design in which no other macros or standard cells can be place.If macros moves halo will also move.
Blockage:- It can be specified for any part of the design.If we move the block blockage will not move.

Q 47.Why we apply NDR rules before routing?
A. Some times with default routing it is very hard to avoid cross talk,electromigration.Fixing the cross-talk,electromigration in routing stage is difficult.So we are applying ndr rules(double space,double width) before routing.

Q 48.What are the types of blockages?
A. Hard blockage:- It does't allow inverters,buffers,standard cells.
Soft blockage:- It allows only inverters and buffers and blocks standard cells.
Partial blockage:- It will allow both buffers and standard cell in a percentage value.

Q 49.What is congestion?
A. When the available tracks are less than the required tracks this effect will occur.When the signals are more than the tracks then congestion will occur.

Q 50.How to fix congestion?
A. 

• Congestion driven placement.
• Adjust cell density in congested area(high cell density cause congestion).
• Use proper blockage.
• Modify the floor plan design.