ASIC design flow

by kamalnadh


               ASIC(Application specific integrated circuit) is designed for a special solo purpose and  the function of chip is same through out the chip life.It's digital circuitry is made up of permanently connected gates and flip flops in silicon so the logic function can't be changed.

specifications:-

             Day by day the technology is increasing and customer also expecting new features(like low power consumption,high speed) in the device.In this stage the features information which is expecting from the customer is collected by some marketing people.

Architecture design:-

             The architecture team will design an architecture based on the specifications.The architecture is like a block diagram we can find the all the details which are using in the design(like processors,memories) and how the are connected.This architecture team will estimate the block area,how much power is required and cost for the design.

RTL design:-

            Register transfer level(RTL) constructing a digital design using combinational and sequential circuit in hardware description language like verilog or VHDL.The above architecture is converted into verilog or VHDL code.This code describes how data is transformed as it is passed from register to register

RTL verification:-
                It is a functional verification of RTL design.After the RTL design by applying test cases we verify the design in verification stage.If any mistakes are found then the design is re send to the RTL designing department.The verification stage will take nearly 60% of the total time.Performing this verification at this stage is most advantageous because correcting the faults at routing stage is difficult and takes more time.

Synthesis:-
               It is a process of converting the RTL code into gate level netlist.Up to RTL verification the design is technology independent.In synthesys process the design is converted into technology dependent.it is 3 stage process.
1.Translation:- The RTL code is converted in to Boolean expression.
2.Optimization:- In this stage Boolean expression is optimized by SOP and POS optimization method.
3.Mapping:- In this technology independent Boolean expression is converted into technology dependent and generates the gate level net list.
The inputs for synthesis are RTL code, .SDC and .LIB.after the synthesis the generated outputs are gate level netlist and .SDC.

DFT:-
         Design for testability(DFT) is a technique which facilitates a design to become testable after production.In this stage we put extra logic along with the design logic during implementation process which helps post production process.The DFT will make the testing easy at post production process.At this stage an ATPG(automatic test pattern generator) file will generated.

Floorplan:-
              The floorplan is the process of determining the macro placement,power grid generation and i/o placement.It is the process of placing blocks/macros in the chip/core area there by determining routing areas between them.It determines the size of the die and creates wire tracks for placement of standard cells.It creates power straps and specifies pg connection.It also determine the i/o ,pin/pad placement information.

Placement:-
          Placement is the process of automatically assigning correct position to standard cells on the chip with no overlapping.By global placement outside of standard cells will placed inside roughly.By the detailed placement the standard cells will place in site rows(legalize placement).In placement stage we check the congestion value by GRC map.

CTS (clock tree synthesis):-
               In this stage we built the clock tree by using inverters and buffers.In the chip clock signal is essential to the flip flops,to give the clock signal from clock source we built the clock tree.It is the process of balancing the clock skew and minimizing insertion delay in order to meet timing and power.
Routing:-

               Before the routing stage the connection between the macros,standard cells,clock,i/o port are logical connections.In this stage we connect all the cells physically with the metal straps.Routing is divided as two parts 1)global routing 2)detailed routing.The global routing will tell for which signal which metal layer is used.Before the detailed routing all are the logical connections.In detailed routing the physical connections are done.

Signoff:-

              After the routing the physical layout of chip is completed.In signoff stage all the tests are done to check the quality and performance of the layout before tapeout.After this the design is converted into GDS II file.

Fabrication:-
                By the GDS II file  information we fabricate the chip.The total design is converted into chip by the manufacturing process.

Packaging and testing:-
             After the fabrication process we test the chip.If there is any fault in the design then we modifies the design by repeating the steps.If there are no faults then chip will go to packaging. 

                              

Physical design flow

by kamalnadh


PD flow:-

Physical design:-  It is the process of transforming a circuit description into physical layout.which describes the position of cells and routes for the interconnection between them.the physical design process stages are listed below.

Import design:-

           It is the first stage in physical design.In synthesis process the RTL code is converted into netlist.In this import design stage all input files are read by the tool.By using this information the design process will starts.

Floorplan:-
            The floorplan is the process of determining the macro placement,power grid generation and i/o placement.It is the process of placing blocks/macros in the chip/core area there by determining routing areas between them.It determines the size of the die and creates wire tracks for placement of standard cells.It creates power straps and specifies pg connection.It also determine the i/o ,pin/pad placement information.

                      

Placement:-
          Placement is the process of automatically assigning correct position to standard cells on the chip with no overlapping.By global placement outside of standard cells will placed inside roughly.By the detailed placement the standard cells will place in site rows(legalize placement).In placement stage we check the congestion value by GRC map.

(Note:- For just understanding purpose standard cell size was increased.in practical standard cell and rows are too small compare to macros.Count of std cells also high.ex:-50k)

CTS(clock tree synthesis):-
               In this stage we built the clock tree by using inverters and buffers.In the chip clock signal is essential to the flip flops,to give the clock signal from clock source we built the clock tree.It is the process of balancing the clock skew and minimizing insertion delay in order to meet timing and power.

Routing:-

               Before the routing stage the connection between the macros,standard cells,clock,i/o port are logical connections.In this stage we connect all the cells physically with the metal straps.Routing is divided as two parts 1)global routing 2)detailed routing.The global routing will tell for which signal which metal layer is used.Before the detailed routing all are the logical connections.In detailed routing the physical connections are done.

Signoff:-
              After the routing the physical layout of chip is completed.In signoff stage all the tests are done to check the quality and performance of the layout before tapeout.

Floorplan

by kamalnadh

                                 Floorplan

                    It is the first stage in the physical design.The quality of floorplan will decide the total chip performance.The floorplan is the process of determining the macro placement,power grid generation and i/o (or) pin placement.
            It is the process of placing blocks/macros in the chip/core area there by determining routing areas between them.It determines the size of the die and creates wire tracks for placement of standard cells.It creates power straps and specifies pg connection.It also determine the i/o,pin/pad placement information.

  Before discussing about floorplan let see few definitions in floor plan.
Macro:- These are special memory elements used to store the data efficiently and also don't occupy much space on the chip comparatively these memory cells are called macros.All memories are macros but all macros are not memories.

Hard macro:- The circuit is fixed and we don't know which type of gates using inside.We know only timing information not the functional information.

Soft macro:- The circuit is not fixed and we know which type of gates using inside.We know timing information and also functional information.

Core:- It is defined as the inner block which contains the std cells and macro.

Die:- It is the block around the core which contain i/o ports.

Halo:- It is the region around the boundary of fixed macros in design in which no other macros or standard cells can be place.If macros moves halo will also move.


Blockage:- It can be specified for any part of the design.If we move the block blockage will not move.

Placement blockage:- It prevents the tool from placing the cells at specific region.

Types of floorplan techniques used in full chip plan:-

  1.Abutted:- When the chip is divided into blocks in abutted design there is no gap between the blocks.

  2.Non abutted:- In this design there is a gap between blocks.The connection between the blocks are done through the routing nets.

  3.Mix of both:- This design is combination of abutted and non- abutted. 

Input files of floorplan:-

•    .v (netlist)
•   .sdc (synthetic design constraints)
•   .lib (logical libraries)
•   .lef (physical libraries)
•   .tf (technology file)
•   .tlu+
•   .tdf

  Steps in floorplan:-

• Giving aspect ratio:- Aspect ratio will decides the size and shape of the chip.It is the ratio between vertical routing resources to horizontal routing resources (or) ratio of height and width.If aspect ratio is 1 that means height and width of the chip is same.If aspect ratio is 0.5 that means width is 2 times of height (height=1,width=2).

                Aspect ratio = Height/width

• Core utilization:- Utilization will defines the area occupied by the standard cells,macros and other cells.If core utilization is 0.7 (70%) that means 70% of core area is use for placing the standard cells,macros and other cell and remaining 30% is used for routing.

         

• Placing macros inside core:- The main step in floorplan is placing the macros inside the core.After giving of aspect ratio and utilization factor chip size and shape was created.All the stranded cells and macros are placed outer side of the chip.In this floor plan stage we have to place the macros by some guide lines like fly line analysis,port communication,macro grouping etc.

            

• Cut the rows on macros:- In floor plan stage rows are created inside the core to place the standard cells.When we place macros inside the chip the rows will over laps the macros.so we need to cut the rows on macros.

• insert physical cells:- Inserting physical cells like tap cells,end cap cells,filler cells etc.These cells will protect the chip from faults. 

• i/o placement:- I/O pads are placed at the boundaries.In block level these i/o pins are placed at input and output side of the block to interact with other blocks and transfer the signals.After that logical cell placement blockage is created in die area to prevent the logical cell placement.The die area is only for the i/o pins.

• creating blockage:- Placement blockage is applied in the floor plan stage to prevent standard cell placement.If we don't apply the placement blockage there is a chance to overlap the standard cells on macros.We applied this at macros area so there is no chance to overlap the standard cells on macros.

Guide lines for macro placement:-

• Flyline analysis.
• Port communication.
• Macro grouping. 
• Spacing between macros.
• Macros placed at boundaries.
• Macro alignment.
• Blockages.
• Avoiding crisscross connections of macros.

Outputs of floorplan:-

• Macro placed.
• Power grid design.
• I/O placed.
• Standard cell placement area.
• Block area.

                                                                Power planning
             
Inputs of power plan:-

• Database with valid floor plan
• Power rings and power straps width
• Spacing between VDD and VSS straps

Few definitions in the power plan:-
Mesh:- Horizontal and vertical power straps in the design are called mesh.

Straps:- Strap is a net(metal layers) which carry the power.

IR drop:- Each metal layer has a resistance value.when the current flows through the metal the resistance consumes some current.This is the IR drop.If the resistance is more the drop also more.

Electromigration(EM):- When high current density continuously flows through a metal due to the high current the atoms moving with kinetic energy and they transfer the energy to another atoms and increases the temperature due to these the metal will damage.

Via:- It is a electrical interaction between the two metal layers.

power planing:-
               Power planing is used to equally distribute the power to the cells (macros,standard cells and other cells) in the chip.Normal power connection will not the distribute the power equally throughout the chip so we choose special power design to chip to carry power throughout the chip equally.In this step there are three levels of power distribution

• Rings
• Straps
• Rails

Rings:- Ring is placed around the chip which carries VDD and VSS
Straps:- It is difficult to transfer the power equally from edge of the chip to center of the chip.so we so we placed horizontal and vertical nets(metal layers) in the chip from the rings to carry the power.
Rails:- This rail will connect the VDD and VSS to Std cells.

In the above fig VDD and VSS are the straps.

  In power planning we mainly concentrates on IR drop and Electromigration. In power planing power is mostly transferring through the power straps.So we have to decrease the IR drop.IR drop is caused by the resistance if the resistance is more then the IR drop also more.Top meta layers will have less resistance so IR drop will decreases so we choose top metal layers.
      How to decrease IR drop:-

•  Adding more straps
•  Increase strap width

Electromigration is leads to damage the metal.When high current flows through the metal layer the atoms in the metal also moves and the temperature will increases which cause the metal damage.so we have to reduce this effect.
        How to fix Electromigration:-
           a) Down size the driver.
          b) Increase the metal width.
          c) Add more vias.
          d) Spread cells.

Outputs of power planning:-

• Design with power structure

                   

     

Routing

by kamalnadh

Routing:-
               Before the routing stage the connection between the macros,standard cells,clock,i/o port are logical connections.In this stage we connect all the cells physically with the metal straps.The routing done in different steps.

Steps in routing:-

   1.Global routing.

   2.Track assignment.

   3.Detailed routing.

   4.Search and repair.

Global routing:- It is done to provide instructions to detailed routing about where to route every net.It  provides the logical connections to all cells.First the design is divided into small boxes which are called Gcell. Each Gcell have the horizontal and vertical routing resources.It's aim is to reduce the total interconnect length and minimize the critical path delay.By using global routing we can analyse congestion.

Track assignment:- It assigns each net to a specific track and lays down the actual metal tracks.

Detailed routing:-   Before detailed routing the connections are logical.In this stage all the cells are physically connected.In this we specifies the wire/interconnection in the channels specified by the global routing.Metal layer information of the interconnections are also specified here.The violations that are created in track assignment are fixed in this stage.It does't route entire chip at a time.By dividing the chip into small boxes(G cells) it will do routing. DRC's are fixed in detailed routing.

Search and repair:- It fixes the remaining DRC violations  through multiple loops using progressive layer Sbox sizes.

Goals of routing:-

• Minimize the total wire length.
• Minimizing the congestion hotspots.
• Reducing the cross-talk.
• Minimizing no.of via's.
• Meeting the timing DRC's.