by kamalnadh
Floorplan
It is the first stage in the physical design.The quality of floorplan will decide the total chip performance.The floorplan is the process of determining the macro placement,power grid generation and i/o (or) pin placement.
It is the process of placing blocks/macros in the chip/core area there by determining routing areas between them.It determines the size of the die and creates wire tracks for placement of standard cells.It creates power straps and specifies pg connection.It also determine the i/o,pin/pad placement information.
Before discussing about floorplan let see few definitions in floor plan.
Macro:- These are special memory elements used to store the data efficiently and also don't occupy much space on the chip comparatively these memory cells are called macros.All memories are macros but all macros are not memories.
Hard macro:- The circuit is fixed and we don't know which type of gates using inside.We know only timing information not the functional information.
Soft macro:- The circuit is not fixed and we know which type of gates using inside.We know timing information and also functional information.
Core:- It is defined as the inner block which contains the std cells and macro.
Die:- It is the block around the core which contain i/o ports.
Halo:- It is the region around the boundary of fixed macros in design in which no other macros or standard cells can be place.If macros moves halo will also move.
Blockage:- It can be specified for any part of the design.If we move the block blockage will not move.
Placement blockage:- It prevents the tool from placing the cells at specific region.
Types of floorplan techniques used in full chip plan:-
1.Abutted:- When the chip is divided into blocks in abutted design there is no gap between the blocks.
2.Non abutted:- In this design there is a gap between blocks.The connection between the blocks are done through the routing nets.
3.Mix of both:- This design is combination of abutted and non- abutted.
Input files of floorplan:-
Steps in floorplan:-
Guide lines for macro placement:-
Outputs of floorplan:-
Power planning
Inputs of power plan:-
Few definitions in the power plan:-
Mesh:- Horizontal and vertical power straps in the design are called mesh.
Straps:- Strap is a net(metal layers) which carry the power.
IR drop:- Each metal layer has a resistance value.when the current flows through the metal the resistance consumes some current.This is the IR drop.If the resistance is more the drop also more.
Electromigration(EM):- When high current density continuously flows through a metal due to the high current the atoms moving with kinetic energy and they transfer the energy to another atoms and increases the temperature due to these the metal will damage.
Via:- It is a electrical interaction between the two metal layers.
power planing:-
Power planing is used to equally distribute the power to the cells (macros,standard cells and other cells) in the chip.Normal power connection will not the distribute the power equally throughout the chip so we choose special power design to chip to carry power throughout the chip equally.In this step there are three levels of power distribution
Straps:- It is difficult to transfer the power equally from edge of the chip to center of the chip.so we so we placed horizontal and vertical nets(metal layers) in the chip from the rings to carry the power.
Rails:- This rail will connect the VDD and VSS to Std cells.
In power planning we mainly concentrates on IR drop and Electromigration. In power planing power is mostly transferring through the power straps.So we have to decrease the IR drop.IR drop is caused by the resistance if the resistance is more then the IR drop also more.Top meta layers will have less resistance so IR drop will decreases so we choose top metal layers.
How to decrease IR drop:-
Electromigration is leads to damage the metal.When high current flows through the metal layer the atoms in the metal also moves and the temperature will increases which cause the metal damage.so we have to reduce this effect.
How to fix Electromigration:-
a) Down size the driver.
b) Increase the metal width.
c) Add more vias.
d) Spread cells.
Floorplan
It is the first stage in the physical design.The quality of floorplan will decide the total chip performance.The floorplan is the process of determining the macro placement,power grid generation and i/o (or) pin placement.
It is the process of placing blocks/macros in the chip/core area there by determining routing areas between them.It determines the size of the die and creates wire tracks for placement of standard cells.It creates power straps and specifies pg connection.It also determine the i/o,pin/pad placement information.
Before discussing about floorplan let see few definitions in floor plan.
Macro:- These are special memory elements used to store the data efficiently and also don't occupy much space on the chip comparatively these memory cells are called macros.All memories are macros but all macros are not memories.
Hard macro:- The circuit is fixed and we don't know which type of gates using inside.We know only timing information not the functional information.
Soft macro:- The circuit is not fixed and we know which type of gates using inside.We know timing information and also functional information.
Core:- It is defined as the inner block which contains the std cells and macro.
Die:- It is the block around the core which contain i/o ports.
Halo:- It is the region around the boundary of fixed macros in design in which no other macros or standard cells can be place.If macros moves halo will also move.
Blockage:- It can be specified for any part of the design.If we move the block blockage will not move.
Placement blockage:- It prevents the tool from placing the cells at specific region.
Types of floorplan techniques used in full chip plan:-
1.Abutted:- When the chip is divided into blocks in abutted design there is no gap between the blocks.
2.Non abutted:- In this design there is a gap between blocks.The connection between the blocks are done through the routing nets.
3.Mix of both:- This design is combination of abutted and non- abutted.
Input files of floorplan:-
- .v (netlist)
- .sdc (synthetic design constraints)
- .lib (logical libraries)
- .lef (physical libraries)
- .tf (technology file)
- .tlu+
- .tdf
Steps in floorplan:-
- Giving aspect ratio:- Aspect ratio will decides the size and shape of the chip.It is the ratio between vertical routing resources to horizontal routing resources (or) ratio of height and width.If aspect ratio is 1 that means height and width of the chip is same.If aspect ratio is 0.5 that means width is 2 times of height (height=1,width=2).
- Core utilization:- Utilization will defines the area occupied by the standard cells,macros and other cells.If core utilization is 0.7 (70%) that means 70% of core area is use for placing the standard cells,macros and other cell and remaining 30% is used for routing.
- Placing macros inside core:- The main step in floorplan is placing the macros inside the core.After giving of aspect ratio and utilization factor chip size and shape was created.All the stranded cells and macros are placed outer side of the chip.In this floor plan stage we have to place the macros by some guide lines like fly line analysis,port communication,macro grouping etc.
- Cut the rows on macros:- In floor plan stage rows are created inside the core to place the standard cells.When we place macros inside the chip the rows will over laps the macros.so we need to cut the rows on macros.
- insert physical cells:- Inserting physical cells like tap cells,end cap cells,filler cells etc.These cells will protect the chip from faults.
- i/o placement:- I/O pads are placed at the boundaries.In block level these i/o pins are placed at input and output side of the block to interact with other blocks and transfer the signals.After that logical cell placement blockage is created in die area to prevent the logical cell placement.The die area is only for the i/o pins.
- creating blockage:- Placement blockage is applied in the floor plan stage to prevent standard cell placement.If we don't apply the placement blockage there is a chance to overlap the standard cells on macros.We applied this at macros area so there is no chance to overlap the standard cells on macros.
Guide lines for macro placement:-
- Flyline analysis.
- Port communication.
- Macro grouping.
- Spacing between macros.
- Macros placed at boundaries.
- Macro alignment.
- Blockages.
- Avoiding crisscross connections of macros.
Outputs of floorplan:-
- Macro placed.
- Power grid design.
- I/O placed.
- Standard cell placement area.
- Block area.
Inputs of power plan:-
- Database with valid floor plan
- Power rings and power straps width
- Spacing between VDD and VSS straps
Few definitions in the power plan:-
Mesh:- Horizontal and vertical power straps in the design are called mesh.
Straps:- Strap is a net(metal layers) which carry the power.
IR drop:- Each metal layer has a resistance value.when the current flows through the metal the resistance consumes some current.This is the IR drop.If the resistance is more the drop also more.
Electromigration(EM):- When high current density continuously flows through a metal due to the high current the atoms moving with kinetic energy and they transfer the energy to another atoms and increases the temperature due to these the metal will damage.
Via:- It is a electrical interaction between the two metal layers.
power planing:-
Power planing is used to equally distribute the power to the cells (macros,standard cells and other cells) in the chip.Normal power connection will not the distribute the power equally throughout the chip so we choose special power design to chip to carry power throughout the chip equally.In this step there are three levels of power distribution
- Rings
- Straps
- Rails
Straps:- It is difficult to transfer the power equally from edge of the chip to center of the chip.so we so we placed horizontal and vertical nets(metal layers) in the chip from the rings to carry the power.
Rails:- This rail will connect the VDD and VSS to Std cells.
In the above fig VDD and VSS are the straps.
How to decrease IR drop:-
- Adding more straps
- Increase strap width
Electromigration is leads to damage the metal.When high current flows through the metal layer the atoms in the metal also moves and the temperature will increases which cause the metal damage.so we have to reduce this effect.
How to fix Electromigration:-
a) Down size the driver.
b) Increase the metal width.
c) Add more vias.
d) Spread cells.
Outputs of power planning:-
- Design with power structure
How will you cut rows on macro placement ? Is there any methods
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