Placement

by kamalnadh

                              Placement
                            
                   Placement is the process of automatically assigning correct position to standard cells on the chip with no overlapping. By global placement outside of standard cells will placed inside roughly.By the detailed placement the standard cells will place in site rows(legalize placement).In placement stage we check the congestion value by GRC map.

Inputs of placement:-

•  Floorplan design.
•  Netlist.
•  Design constraints.
•  Logical library(.lib),physical library(.lef).

Before discussing about placement let see few definitions in placement.

Blockage:- Blocking a specific are to prevent placing of cells.

Hard blockage:- It does't allow inverters,buffers,standard cells.

Soft blockage:- It allows only inverters and buffers and blocks standard cells.

Partial blockage:- It will allow both buffers and standard cell in a percentage value.

Congestion:- when the available tracks are less than the required tracks this effect will occur.When the signals are more than the tracks then congestion will occur.

HFNS (high fan-out net synthesis ):- HFNS is the process of buffering the high fan-out nets to balance the load.

Scan chain:- It is used in design for testing.It makes testing easier by setting a group of Flip-flops connecting serially.

Goals of placement:-

• Minimum congestion.
• Minimum timing DRC's.
• Timing power and area optimization.
• Minimum cell density,pin density and congestion hotspots.

Process in the placement:-

• Course placement:- In floor plan stage we place only macros inside the chi.In placement we place standard cells inside the core.by the course placement outside of standard cells will place inside roughly.

       

(Note:- for just understanding purpose standard cell size was increased.in practical standard cell and rows are too small compare to macros)

• Legalize placement:- By the course placement standard cells overlaps on the rows.To fix this we are doing legalize placement.by this legalize placement all the standard cells are fixed in rows

        

(Note:- for just understanding purpose standard cell size was increased.in practical standard cell and rows are too small compare to macros)

• Congestion analysis:- when available tracks are less then the required tracks then congestion will occur.The congestion range can be estimated by GRC map.

       Congestion reduction techniques:-

       a) Congestion driven placement.

       b) Adjust cell density in congested area(high cell density cause            congestion).

       c) Use proper blockage.

       d) Modify the floor plan design.

• Blockage:- To reduce the congestion we have to use proper blockage.There are three types of blockages hard blockage,soft blockage and partial blockage.By the blockage cells will not overlap.Macro padding and cell padding are the placement blockages.In macro padding the area around the macro is blocked so no std cells will place near to macro.

• HFNS (high fan-out net synthesis):- Fan-out is the maximum number of inputs that a single output of logic gate.To balance the load HFNS is performed.Too many loads will effects the delay numbers and transition time.because load is directly proportional to load.by buffering the HFN the load can be balanced. 

• placement optimization:- It can be done by different options like area recovery,DFT,power,congestion and timing.By using power option we can reduce the static and dynamic power consumpion.By using area recovery we can reduce the cells,power and timing.By scan chain reordering(DFT) we can reduce the routing length. 

Scan chain reordering:- 
                 Scan chain  is used in design for testing.It makes testing easier by setting a group of Flip-flops connecting serially.but in placement stage all the flip-flops are not placed serially (ex:- FF 1 is placed at one corner and FF 2 is placed another corner) but scan chain will connect serially like FF 1 to FF 2 to FF 3.this will leads to increase in routing length and crisscross connection then congestion will increase.In order to decrease this crisscross connection and routing length we are doing scan chain reordering.In this the FF 1 will connect to nearer flip-flop.which will reduce crisscross connections.By the scan chain reordering congestion will reduce but some time it will increase hold time problem in the chain.To over come this buffers inserted in scan path.

Fig 1

Fig 2

Fig 1 shows before scan chain reordering flip-flops are connected serially like FF1-FF2-FF3-FF4. This will increase the routing length and crisscross connections (congestion).
Fig2 shows after scan chain reordering flip-flops are connected nearer by them like FF1-FF3-FF2-FF4. This will decrease the routing length and congestion also decreases.

Power optimization:-
      Now a days most of devices targeted to consume less power because consumers also expecting less power power consumption devices.We have two types of power dissipation.

Static power dissipation:- It is also called leakage power.It can be reduced by replacing LVT cells with HVT cells in a percentage.Because HVT cells have less leakage power.Some architectures will use power gating to reduce static power.

Dynamic power dissipation:- Dynamic power dissipation is due to load and high switching activities.These power can be reduced by reducing the load capacitance,cell sizing,sharing the load.


Outputs of placement:-

• Timing information.
• Congestion report.
• Physical layout information.
• Cell placement location.