Physical design flow

by kamalnadh


PD flow:-

Physical design:-  It is the process of transforming a circuit description into physical layout.which describes the position of cells and routes for the interconnection between them.the physical design process stages are listed below.

Import design:-

           It is the first stage in physical design.In synthesis process the RTL code is converted into netlist.In this import design stage all input files are read by the tool.By using this information the design process will starts.

Floorplan:-
            The floorplan is the process of determining the macro placement,power grid generation and i/o placement.It is the process of placing blocks/macros in the chip/core area there by determining routing areas between them.It determines the size of the die and creates wire tracks for placement of standard cells.It creates power straps and specifies pg connection.It also determine the i/o ,pin/pad placement information.

                      

Placement:-
          Placement is the process of automatically assigning correct position to standard cells on the chip with no overlapping.By global placement outside of standard cells will placed inside roughly.By the detailed placement the standard cells will place in site rows(legalize placement).In placement stage we check the congestion value by GRC map.

(Note:- For just understanding purpose standard cell size was increased.in practical standard cell and rows are too small compare to macros.Count of std cells also high.ex:-50k)

CTS(clock tree synthesis):-
               In this stage we built the clock tree by using inverters and buffers.In the chip clock signal is essential to the flip flops,to give the clock signal from clock source we built the clock tree.It is the process of balancing the clock skew and minimizing insertion delay in order to meet timing and power.

Routing:-

               Before the routing stage the connection between the macros,standard cells,clock,i/o port are logical connections.In this stage we connect all the cells physically with the metal straps.Routing is divided as two parts 1)global routing 2)detailed routing.The global routing will tell for which signal which metal layer is used.Before the detailed routing all are the logical connections.In detailed routing the physical connections are done.

Signoff:-
              After the routing the physical layout of chip is completed.In signoff stage all the tests are done to check the quality and performance of the layout before tapeout.

Placement

by kamalnadh

                              Placement
                            
                   Placement is the process of automatically assigning correct position to standard cells on the chip with no overlapping. By global placement outside of standard cells will placed inside roughly.By the detailed placement the standard cells will place in site rows(legalize placement).In placement stage we check the congestion value by GRC map.

Inputs of placement:-

•  Floorplan design.
•  Netlist.
•  Design constraints.
•  Logical library(.lib),physical library(.lef).

Before discussing about placement let see few definitions in placement.

Blockage:- Blocking a specific are to prevent placing of cells.

Hard blockage:- It does't allow inverters,buffers,standard cells.

Soft blockage:- It allows only inverters and buffers and blocks standard cells.

Partial blockage:- It will allow both buffers and standard cell in a percentage value.

Congestion:- when the available tracks are less than the required tracks this effect will occur.When the signals are more than the tracks then congestion will occur.

HFNS (high fan-out net synthesis ):- HFNS is the process of buffering the high fan-out nets to balance the load.

Scan chain:- It is used in design for testing.It makes testing easier by setting a group of Flip-flops connecting serially.

Goals of placement:-

• Minimum congestion.
• Minimum timing DRC's.
• Timing power and area optimization.
• Minimum cell density,pin density and congestion hotspots.

Process in the placement:-

• Course placement:- In floor plan stage we place only macros inside the chi.In placement we place standard cells inside the core.by the course placement outside of standard cells will place inside roughly.

       

(Note:- for just understanding purpose standard cell size was increased.in practical standard cell and rows are too small compare to macros)

• Legalize placement:- By the course placement standard cells overlaps on the rows.To fix this we are doing legalize placement.by this legalize placement all the standard cells are fixed in rows

        

(Note:- for just understanding purpose standard cell size was increased.in practical standard cell and rows are too small compare to macros)

• Congestion analysis:- when available tracks are less then the required tracks then congestion will occur.The congestion range can be estimated by GRC map.

       Congestion reduction techniques:-

       a) Congestion driven placement.

       b) Adjust cell density in congested area(high cell density cause            congestion).

       c) Use proper blockage.

       d) Modify the floor plan design.

• Blockage:- To reduce the congestion we have to use proper blockage.There are three types of blockages hard blockage,soft blockage and partial blockage.By the blockage cells will not overlap.Macro padding and cell padding are the placement blockages.In macro padding the area around the macro is blocked so no std cells will place near to macro.

• HFNS (high fan-out net synthesis):- Fan-out is the maximum number of inputs that a single output of logic gate.To balance the load HFNS is performed.Too many loads will effects the delay numbers and transition time.because load is directly proportional to load.by buffering the HFN the load can be balanced. 

• placement optimization:- It can be done by different options like area recovery,DFT,power,congestion and timing.By using power option we can reduce the static and dynamic power consumpion.By using area recovery we can reduce the cells,power and timing.By scan chain reordering(DFT) we can reduce the routing length. 

Scan chain reordering:- 
                 Scan chain  is used in design for testing.It makes testing easier by setting a group of Flip-flops connecting serially.but in placement stage all the flip-flops are not placed serially (ex:- FF 1 is placed at one corner and FF 2 is placed another corner) but scan chain will connect serially like FF 1 to FF 2 to FF 3.this will leads to increase in routing length and crisscross connection then congestion will increase.In order to decrease this crisscross connection and routing length we are doing scan chain reordering.In this the FF 1 will connect to nearer flip-flop.which will reduce crisscross connections.By the scan chain reordering congestion will reduce but some time it will increase hold time problem in the chain.To over come this buffers inserted in scan path.

Fig 1

Fig 2

Fig 1 shows before scan chain reordering flip-flops are connected serially like FF1-FF2-FF3-FF4. This will increase the routing length and crisscross connections (congestion).
Fig2 shows after scan chain reordering flip-flops are connected nearer by them like FF1-FF3-FF2-FF4. This will decrease the routing length and congestion also decreases.

Power optimization:-
      Now a days most of devices targeted to consume less power because consumers also expecting less power power consumption devices.We have two types of power dissipation.

Static power dissipation:- It is also called leakage power.It can be reduced by replacing LVT cells with HVT cells in a percentage.Because HVT cells have less leakage power.Some architectures will use power gating to reduce static power.

Dynamic power dissipation:- Dynamic power dissipation is due to load and high switching activities.These power can be reduced by reducing the load capacitance,cell sizing,sharing the load.


Outputs of placement:-

• Timing information.
• Congestion report.
• Physical layout information.
• Cell placement location.

CTS

by kamalnadh

                                   CTS
        In this stage we built the clock tree by using inverters and buffers.In the chip clock signal is essential to the flip flops,to give the clock signal from clock source we built the clock tree.It is the process of balancing the clock skew and minimizing insertion delay in order to meet timing and power.

 Before discussing about CTS let see few definitions in CTS.

Aggressor:- A net which creates the effect on nearer net(victim).

Victim:- A net which receives the effect from nearer net(aggressor).

Shielding:- Placing ground net in between aggressor and victim net then voltage discharge on ground net.This will reduce cross-talk.

Cross-talk:- It is the undesirable electric interaction between two or more physical adjust nets due to the capacitance cross coupling.

CTO(clock tree optimization):- It improves the clock skew and clock insertion delay by applying additional optimization. CTO is performed during clock_opt process.

Inputs required for cts:-

• Detailed placement database.
• Target for latency and skew if specified.
• Buffers or inverters for building the clock tree.
• Clock tree DRC's.

Checks before cts:-

• Completed placement.
• Power ground nets - pre routed.
• Acceptable congestion.
• Estimated timing.
• HFNS.

Process:-

      It is a process of inserting buffers and inverters along with the clock path to balance the delay to all clock inputs. Before CTS we treat clock as ideal.If we did't built the clock the skew and insertion delay will increases.This will effects the chip performance.To overcome this we are constructing the clock tree by using inverters and buffers.Below fig shows the structure of before CTS and after CTS.

    Fig:-Before CTS

Fig:-After CTS

Clock tree optimization (CTO):-

It improves the clock skew and clock insertion delay by applying additional optimization. CTO is performed during clock_opt process.The CTO techniques are listed below

Delay insertion:- It will improve hold time.

Buffering:- It will improve setup time.

Buffer relocation:- Reduce skew and insertion delay.

Level adjustment:- Adjust a level of clock pins to a higher or lower

Gate sizing:- It may decrease the delay.

To fix max transition add buffers and to fix max capacitance decrease the net length,cloning.

NDR's:-
Non default rules are applied to reduce the cross-talk and electromigration.NDR's like double spacing,double width shielding.
By applying double spacing cross-talk will reduce.
By applying double width we can avoid electromigration.

Cross-talk:- 

          It is the undesirable electric interaction between two or more physical adjust nets due to the capacitance cross coupling.when two nets are in parallel the electric field of one net is effects the other net which is nearer to it.This called cross-talk effect.

The above fig explain the cross-talk effect.There are two nets running parallel and spacing between the nets are less so capacitance is more.The input of aggressor net inverter is falling signal and the output is raising edge.The input of victim net inverter is raising signal and the output is falling signal.When the rising edge signal is entering into the aggressor net 2nd inverter the charge will stores in the capacitance due to electrical interference at the same time the charge stored in the capacitance will discharge on falling signal of victim net 2nd inverter input.Due to this the falling signal will effect.Here 1st net is creating the effect so that is aggressor and second net receiving effect so that is victim.

Cross-talk reducing techniques:-
a) Increase the spacing between the aggressor and victim nets.
b) Shielding.
c) Maintain the stable supply.
d) Increase the drive strength of cell.
e) Layer jumping.
f) Victim net width increasing then resistance decreases.
g) Guard ring.
h) Cell sizing (up sizing).

CTS exceptions:-

Stop pins:- These are the end point of clock tree and used in calculation and optimization of DRC and clock tree timing(skew,insertion delay).

Float pins:- It's like stop pins with additional delay.

Exclude pins:- It is used only in calculation and optimization of DRC's.It not target skew and insertion delay.


Checklist after cts:-

• Skew report.
• Clock tree report.
• Timing report for setup and hold.
• Power and area report.

CTS goals:-

• Balancing the skew.
• Minimizing insertion delay.
• Minimizing power dissipation.
• Meet the logical DRC's.