PD interview questions and answers - part 3

by kamalnadh

1. What are the types of operating modes?
A. a) Test mode.
     b) Scan mode.
     c) Reset mode.
     d) Functional mode.

2. What is test mode and functional mode?
A. Test mode will detects manufacturing faults after fabrication and functional mode will detects faults at logic.

3.  What is Test clock?
A. If there is a separate clock for scan mode then that clock is known as Test clock.

4. What are the types of timing modes?
A. a) Single mode :- setup and hold check with a single library.
     b) Best case/Worst case mode :- setup with worst case mode and hold with best case mode.
     c) On chip variation mode :- setup and hold check with best case mode(lib1) and worst case mode(lib2)

5. How can you know your netlist is good or bad?
A. If given netlist has buffering on clock and reset then it is not a good netlist.

6. What is FIRE ICE?
A. Fast Interconnect Resistance Extractor Interconnect Capacitance Extractor(FIRE ICE) is a tool for RC extraction.

7. What is Tap current?
A. It is the current drawn by the each and every transistor or standard cell.Based on width of standard cell we can calculate the current value this current is known as tap current.

8. What is the manufacturing grid value?
A. It is the minimum value anything which is less than manufacturing grid value can't be read.

9. Why we use layer map file?
A. It is used for interaction(mapping) between the QRC tech file and tech lef.QRC tech file and lef file contains different names for same metals to over come this problem we use layer map file.

10. What is delay cell?
A. To fix hold tool will add cells in data path these cells are known as delay cells.It just produce output same as input with some delay.

11. What is timing window?
A. Difference between early arrival time and late arrival time for each and every net is known as timing window.

12. Is all the glitches are harmful?
A. All the glitches are not harmful.The glitches whose amplitude is more than VIL(low input voltage) then it will cause problem.

13. What is LEC check?
A. Optimized netlist must checked with final RTL netlist whether  they are logically matched or not.

14. What are the types of wire load models?
A. a) Zero wire load model.
     b) Standard wire load model.
     c) Customized wire load model.
     d) Auto wire load model.

15. Why we don't use HVT cells in lower technologies?
A. HVT cells responds to temperature inversion more effectively.so we don't use HVT cells.

16. What is physical knowledgeable synthesis?
A. After completion of floor plan and placement giving this information to logic synthesis is known as  physical knowledgeable synthesis.

17. What is Steiner?
A. Routing the design with shortest path instead of H-V-H-V(horizontal vertical horizontal vertical) function(this is illegal ).

18. What is top-down methodology?
A. In this we need to synthesis entire RTL code of chip in a single slot.

19. What is black box?
A. In bottom-up approach if A&C block timing is closed but we are still working on B block then make B block as black box.

20. What is the tool used for Rc extraction?
A. Cadence :- QRC.
     Synopsys :- Star RC.

21. What is the tool used for Signoff?
A. Cadence :- ETS.
      Synopsys : Prime Time.

22. What is the tool used for Physical verification?
A. Cadence :- Assura.
     Synopsys :- Hercules.

23. What is the tool used for Logical synthesis?
A. Cadence :- RTL compiler.
     Synopsys :- Design compiler.

24. What is the tool used for Physical synthesis?
A. Cadence :- Encounter gps,pks.
     Synopsys :- Physical compiler.

25. What is the tool used for PNR?
A. Cadence :- SOC encounter.
     Synopsys :- IC compiler.

ASIC design flow

by kamalnadh


               ASIC(Application specific integrated circuit) is designed for a special solo purpose and  the function of chip is same through out the chip life.It's digital circuitry is made up of permanently connected gates and flip flops in silicon so the logic function can't be changed.

specifications:-

             Day by day the technology is increasing and customer also expecting new features(like low power consumption,high speed) in the device.In this stage the features information which is expecting from the customer is collected by some marketing people.

Architecture design:-

             The architecture team will design an architecture based on the specifications.The architecture is like a block diagram we can find the all the details which are using in the design(like processors,memories) and how the are connected.This architecture team will estimate the block area,how much power is required and cost for the design.

RTL design:-

            Register transfer level(RTL) constructing a digital design using combinational and sequential circuit in hardware description language like verilog or VHDL.The above architecture is converted into verilog or VHDL code.This code describes how data is transformed as it is passed from register to register

RTL verification:-
                It is a functional verification of RTL design.After the RTL design by applying test cases we verify the design in verification stage.If any mistakes are found then the design is re send to the RTL designing department.The verification stage will take nearly 60% of the total time.Performing this verification at this stage is most advantageous because correcting the faults at routing stage is difficult and takes more time.

Synthesis:-
               It is a process of converting the RTL code into gate level netlist.Up to RTL verification the design is technology independent.In synthesys process the design is converted into technology dependent.it is 3 stage process.
1.Translation:- The RTL code is converted in to Boolean expression.
2.Optimization:- In this stage Boolean expression is optimized by SOP and POS optimization method.
3.Mapping:- In this technology independent Boolean expression is converted into technology dependent and generates the gate level net list.
The inputs for synthesis are RTL code, .SDC and .LIB.after the synthesis the generated outputs are gate level netlist and .SDC.

DFT:-
         Design for testability(DFT) is a technique which facilitates a design to become testable after production.In this stage we put extra logic along with the design logic during implementation process which helps post production process.The DFT will make the testing easy at post production process.At this stage an ATPG(automatic test pattern generator) file will generated.

Floorplan:-
              The floorplan is the process of determining the macro placement,power grid generation and i/o placement.It is the process of placing blocks/macros in the chip/core area there by determining routing areas between them.It determines the size of the die and creates wire tracks for placement of standard cells.It creates power straps and specifies pg connection.It also determine the i/o ,pin/pad placement information.

Placement:-
          Placement is the process of automatically assigning correct position to standard cells on the chip with no overlapping.By global placement outside of standard cells will placed inside roughly.By the detailed placement the standard cells will place in site rows(legalize placement).In placement stage we check the congestion value by GRC map.

CTS (clock tree synthesis):-
               In this stage we built the clock tree by using inverters and buffers.In the chip clock signal is essential to the flip flops,to give the clock signal from clock source we built the clock tree.It is the process of balancing the clock skew and minimizing insertion delay in order to meet timing and power.
Routing:-

               Before the routing stage the connection between the macros,standard cells,clock,i/o port are logical connections.In this stage we connect all the cells physically with the metal straps.Routing is divided as two parts 1)global routing 2)detailed routing.The global routing will tell for which signal which metal layer is used.Before the detailed routing all are the logical connections.In detailed routing the physical connections are done.

Signoff:-

              After the routing the physical layout of chip is completed.In signoff stage all the tests are done to check the quality and performance of the layout before tapeout.After this the design is converted into GDS II file.

Fabrication:-
                By the GDS II file  information we fabricate the chip.The total design is converted into chip by the manufacturing process.

Packaging and testing:-
             After the fabrication process we test the chip.If there is any fault in the design then we modifies the design by repeating the steps.If there are no faults then chip will go to packaging. 

                              

PD interview questions and answers -part 2

by kamalnadh

Q 1.What are the types in physical verification?
 A. LVS (layout vs schematic).
      DRC (design rule constrain check).
      ERC (electric rule check).
      LEC (logical equivalence check).

Q 2.How to fix setup and hold violations at a time?
A. It is not possible to fix both at a time because if we increase the delay in data path it's good for hold and bad for setup.But there is only one way to fix it.

• Buffer the data path for hold fix.
• Slow the clock frequency for setup fix (this is not a valid fix,but we don't have other option).

Q 3.How can you avoid cross-talk?
A. a) Increase the spacing between the aggressor and victim nets.
     b) Shielding.
     c) Maintain the stable supply.
     d) Increase the drive strength of cell.
     e) Layer jumping.
     f) Victim net width increasing then resistance decreases.
     g) Guard ring.
     h) Cell sizing (up sizing).


Q 4.What is cross-talk?

A. It is the undesirable electric interaction between two or more physical adjust nets due to the capacitance cross coupling.When two nets are in parallel the electric field of one net is effects the other net which is nearer to it.This called cross-talk effect. 

Q 5.What is scan chain reordering?

A. It is the process of re connecting the scan chains in the design to optimize for routing by reordering the scan chain connection which improves timing and congestion.

Q 6.What is the concept of rows in the floor plan?
A. The std-cells in the design are placed in rows.All rows have equal height and spacing.The width of the row can vary.The std-cell in the row get the power and ground connection from vdd and vss rails.Sometimes technology allows the rows to be flip.So they can share the power  and ground rails in vdd-vss-vdd patron.


Q 7.What are the advantages of NDR's?
A. a) By applying the double width we can avoid the EM.
     b) By applying double spacing we can avoid the cross-talk.
     c) Help's to avoid congestion at lower metal layer.
     d) Help's pin accessibility of std-cells .

Q 8.What is temperature inversion?
 A. At higher CMOS technologies cell delay increases when temperature increases.But when you are in lower technologies i.e below 65nm cell delay has inversely proportional to temperature.

Q 9.In reg to reg path if you have setup problem where will you insert buffer?
A. We can insert buffer near to launch flop which decreases the transition time.Hence decreasing the wire delay therefore overall delay will decrease.When arrival time will decrease setup violations will reduce(required time-arrival time).

Q 10.What is partitioning?
A. It is the process of dividing the chip into small blocks this is done mainly to separate different functional blocks and also make placement.routing easier.

Q 11.How can you reduce dynamic power?
A. a) Reduce power supply voltage.
     b) Reduce voltage swing in all nodes.
     c) Reduce the switching probability (transition factor).
     d) Reduce load capacitance.

Q 12. Why double via insertion?
A. To reduce the yield loss due to via failures,double via's are inserted traditionally double via's where inserted in post route and then modify the routing to fix any DRC's.

Q 13.What is metal fill insertion?
A. At the time of etching they use some type of chemicals due to that chemical metal loss will be more for that reaction we are inserting the metal fills.

Q 14.What is metal slotting?
A. It is the Technic for avoiding the problems like metal lift off and metal erosion.

Q 15.What are the power dissipation components?
A. Dynamic power consumption:- Occurs when signals which go through the CMOS circuit change there logic state by charging discharging of o/p node capacitor.
static (leakage power consumption):- It is the power consumed by the sub threshold currents and by reverse biased diodes in a CMOS transistor.
short circuit power consumption:- It occurs during switching on both the NMOS and PMOS transistors in the circuit and they conduct simultaneously for a short amount of time.

Q 16.What is dishing effect?
A. It is defined as the difference between the height of the oxide in the spaces and that of the metal in the trenches.It is caused by CMP.It may reduced by some dummy fill Technics effectively.

Q 17.What is CMP (chemical mechanical polishing)?
A. It is the process of smoothing surface with the combination of chemical and mechanical forces.It is used in IC fabrication to get a high level of polarization.

Q 18.What is the use of placement blockage?
A. a) Defines std-cell and macro area.
     b) Reserve channels for buffer insertion.
     c) Prevent cells from being placed at or near macros.
     d) Prevent congestion near macros.

Q 19.What are the types of global routing?
A. a) Time driven global routing.
     b) Cross-talk driven global routing.
     c) Incremental global routing.

Q 20.What are the violations solved in LVS?
A. a) Shorts.
     b) Opens.
     c) Missing text layers.
     d) Missing lib in GDS.
     e) Missing soft layers.

Q 21.What is the clock latency?
A.It is the delay between the clock source and clock pin.It is two types.Clock source latency and clock network latency.The time taken from clock source to definition pin is the clock source latency and from the clock definition pin to clock pin of the flip flop 2 is the clock network latency.

Q 22.How to fix setup and hold violations?
A. Setup:-

• Reduce the amount of buffers in the path.
• Replace buffers with 2 inverters.
• Replace HVT cells with LVT cells.
• Increase the drive size/strength.
• Insert repeaters.
• Adjust cell position in layout.

     Hold:-

• By adding delay in data path.
• Decrease the drive strength in data path.

Q 23.What are the inputs of floor plan?

A.

• .v
• .lib and .lef
• .sdc
•  tlu+ file
•  Physical partitioning information of design.
•  Floor plan parameters like height,width,aspect ratio,utilization.
•  Pin/pad position.

Q 24.What are the outputs of floor plan?
A. 

• Die/block area.
•  I/O pad placed.
•  Macro placed.
•  Power grid design.
•  Power pre routing.
•  Std-cell placement area.

Q 25.What is keep-out margin?
A. It is the region around the boundary of fixed macros in design in which no other macros or standard cells not allows.It allows only buffers and inverters in it's area.

Q 26.How will you synthesize clock tree?
A.a) Single clock-normal synthesis and optimization.
    b) Multiple clocks-synthesis each clock separately.
    c) Multiple clocks with domine crossing synthesis each clock                separately and balance the skew.

Q 27.What is IR drop?
A. Each metal layer has a resistance value.When the current flows through the metal the resistance consumes some current.This is the IR drop.If the resistance is more the drop also more.

Q 28.how to reduce power dissipation using HVT and LVT in the design?
A.If we have positive slack use HVT cells in the path and use LVT cells in the path when we have negative slack.HVT cells have large delay and less leakage power. LVT cells have less delay and      more leakage power.To meet the timing use LVT cells and to reduce the leakage power use HVT cells.


Q 29.What is wire load model (WLM)?
A. It is an estimation of delay based on area and fan-out.The delay depend on..
     Resistance.
     Capacitance.
     Area of the nets.

Q 30.What is signal integrity?
A. It is the ability of an electric signal to carry information reliably and to resist the effects (cross-talk, EM) of high frequency electromagnetic interface from near by signals.

Q 31.Doe's cross-talk always cause violations?
A.Yes it is because cross-talk adds or subtracts energy to the signal which cause setup or hold violations.

Q 32.How a positive or negative edge triggered flip flop will effect the setup and hold violations?
A. Positive edge triggered flip flop will favour to setup (setup violations will reduce).Negative edge triggered flip flop will favour to hold (hold violations will reduce).

Q 33.What are the i/p's and o/p's of power planing?
A. i/p's:-

• Data base with valid floor plan.
• Power rings and power straps width.
• Spacing between vdd and vss straps.

     o/p:-

• Design with power structure.

Q 34.What are the i/p's and o/p's of placement?
A. I/P's:-

• Netlist.
• Mapped and floor planed design.
• Logical and physical lib.
• Design constraints.

    O/P 's:-

• Physical layout information.
• Cell placement location.
• Physical layout,timing and technical information of lib.

Q 35.If we increase the fan-out of the cell how it will effects delay?
A. Fan-out lead to increased capacitive load on the driving gate.Therefore longer propagation delay.

Q 36.What is multi driven nets?
A. It can be created in RTL by introducing drivers of same or different signal strengths.However during a net with multiple signals are not considered as a good practice.This could lead to failure in a post silicon verification as the driver strength can potentially get heavily altered during manufacturing defects.Many EDA tools don't allow multi driven nets in the design and the designers are expected to remove all multi driven nets from the design.

Q 37.What is magnetic placement?
A. To improve the timing for the design or to improve the congestion for a complex floor plan we can use magnetic placement to specify fixed objects as magnets and icc moves their connected standard cells close to them.For the best results perform the magnetic placement before standard cells are placed.

Q 38.What is lookup table?
A.The table is drawn by using input transition and output load values.It is used to calculate the cell delay.

Q 39.What does we do for low power design?
A. We apply low power techniques

• Clock gating.
• Multi voltage design.
• Power gating.
• Multiple vt libraries.

Q 40.What are the types of checks done in prime time?
A. a) Timing (setup,hold,transition).
     b) Design constraints.
     c) Nets.
     d) Noise.
     e) Clock skew.

Q 41.What analysis we do during floor plan?
A.a) Overlapping of macros.
     b) Allowable IR drop.
     c) Global route congestion.
     d) Physical information of the design.

Q 42. What are the different types of delay models?
A. a) WLM (wire load model)
     b) NLDM ( non linear delay model)
     c) CCS (composite current source)

Q 43.Where placement blockage is created?
A. At floor plan stage it acts like guidelines for placement of standard cells.In CTS stage in order to balance the skew more  no.of buffers and inverters are added and blockages are used to reserve space for buffer and inverter.

Q 44.Why we apply NDR's in placement?
A. Applying NDR's in placement because of avoiding congestion and timing problem.These problems are difficult to fix at routing.These are special rules like double spacing and double width.

Q 45.What is mesh?
A. The horizontal and vertical power straps in the design are called mesh.

Q 46.Why I/O cells are placed in the design?
A. The i/o cells are the one which interact in between the blocks outside of the chip to internal blocks of the chip.In floor plan stage i/o cells are placed in between core and die.These are responsible for providing voltage to the cell in the core.

Q 47.What are the complex cells in the floor plan?
A.These are the cells which are made of group of std-cells based on functionality requirement.This cells height is grater than the std-cells and lesser than the macros.

Q 48.How to fix Electromigration (EM)?
A. a) Down size the driver.
     b) Increase the metal width.
     c) Add more vias.
     d) Spread cells.

Q 49.What is etching?
A.It is used in micro-fabrication to chemically remove layers from the surface of the wafer during manufacturing.

Q 50.What is SOI technology?
A.It refers to use of layered silicon insulator.It reduces leakage current and lower power consumption.

Q 51.What is aggressor and victim?
A.these two terms will come in cross-talk concept.
    Aggressor:- A net which create the effect on nearer net(victim).
    victim:- A net which receives the effect from nearer net(aggressor).

Q 52. What is Mealy and Moore?
A. Mealy:- The outputs are depends on input and present state.
     Moore:- The outputs are depends on only present state.