by kamalnadh
1. What are the types of operating modes?
A. a) Test mode.
b) Scan mode.
c) Reset mode.
d) Functional mode.
2. What is test mode and functional mode?
A. Test mode will detects manufacturing faults after fabrication and functional mode will detects faults at logic.
3. What is Test clock?
A. If there is a separate clock for scan mode then that clock is known as Test clock.
4. What are the types of timing modes?
A. a) Single mode :- setup and hold check with a single library.
b) Best case/Worst case mode :- setup with worst case mode and hold with best case mode.
c) On chip variation mode :- setup and hold check with best case mode(lib1) and worst case mode(lib2)
5. How can you know your netlist is good or bad?
A. If given netlist has buffering on clock and reset then it is not a good netlist.
6. What is FIRE ICE?
A. Fast Interconnect Resistance Extractor Interconnect Capacitance Extractor(FIRE ICE) is a tool for RC extraction.
7. What is Tap current?
A. It is the current drawn by the each and every transistor or standard cell.Based on width of standard cell we can calculate the current value this current is known as tap current.
8. What is the manufacturing grid value?
A. It is the minimum value anything which is less than manufacturing grid value can't be read.
9. Why we use layer map file?
A. It is used for interaction(mapping) between the QRC tech file and tech lef.QRC tech file and lef file contains different names for same metals to over come this problem we use layer map file.
10. What is delay cell?
A. To fix hold tool will add cells in data path these cells are known as delay cells.It just produce output same as input with some delay.
11. What is timing window?
A. Difference between early arrival time and late arrival time for each and every net is known as timing window.
12. Is all the glitches are harmful?
A. All the glitches are not harmful.The glitches whose amplitude is more than VIL(low input voltage) then it will cause problem.
13. What is LEC check?
A. Optimized netlist must checked with final RTL netlist whether they are logically matched or not.
14. What are the types of wire load models?
A. a) Zero wire load model.
b) Standard wire load model.
c) Customized wire load model.
d) Auto wire load model.
15. Why we don't use HVT cells in lower technologies?
A. HVT cells responds to temperature inversion more effectively.so we don't use HVT cells.
16. What is physical knowledgeable synthesis?
A. After completion of floor plan and placement giving this information to logic synthesis is known as physical knowledgeable synthesis.
17. What is Steiner?
A. Routing the design with shortest path instead of H-V-H-V(horizontal vertical horizontal vertical) function(this is illegal ).
18. What is top-down methodology?
A. In this we need to synthesis entire RTL code of chip in a single slot.
19. What is black box?
A. In bottom-up approach if A&C block timing is closed but we are still working on B block then make B block as black box.
20. What is the tool used for Rc extraction?
A. Cadence :- QRC.
Synopsys :- Star RC.
21. What is the tool used for Signoff?
A. Cadence :- ETS.
Synopsys : Prime Time.
22. What is the tool used for Physical verification?
A. Cadence :- Assura.
Synopsys :- Hercules.
23. What is the tool used for Logical synthesis?
A. Cadence :- RTL compiler.
Synopsys :- Design compiler.
24. What is the tool used for Physical synthesis?
A. Cadence :- Encounter gps,pks.
Synopsys :- Physical compiler.
25. What is the tool used for PNR?
A. Cadence :- SOC encounter.
Synopsys :- IC compiler.
1. What are the types of operating modes?
A. a) Test mode.
b) Scan mode.
c) Reset mode.
d) Functional mode.
2. What is test mode and functional mode?
A. Test mode will detects manufacturing faults after fabrication and functional mode will detects faults at logic.
3. What is Test clock?
A. If there is a separate clock for scan mode then that clock is known as Test clock.
4. What are the types of timing modes?
A. a) Single mode :- setup and hold check with a single library.
b) Best case/Worst case mode :- setup with worst case mode and hold with best case mode.
c) On chip variation mode :- setup and hold check with best case mode(lib1) and worst case mode(lib2)
5. How can you know your netlist is good or bad?
A. If given netlist has buffering on clock and reset then it is not a good netlist.
6. What is FIRE ICE?
A. Fast Interconnect Resistance Extractor Interconnect Capacitance Extractor(FIRE ICE) is a tool for RC extraction.
7. What is Tap current?
A. It is the current drawn by the each and every transistor or standard cell.Based on width of standard cell we can calculate the current value this current is known as tap current.
8. What is the manufacturing grid value?
A. It is the minimum value anything which is less than manufacturing grid value can't be read.
9. Why we use layer map file?
A. It is used for interaction(mapping) between the QRC tech file and tech lef.QRC tech file and lef file contains different names for same metals to over come this problem we use layer map file.
10. What is delay cell?
A. To fix hold tool will add cells in data path these cells are known as delay cells.It just produce output same as input with some delay.
11. What is timing window?
A. Difference between early arrival time and late arrival time for each and every net is known as timing window.
12. Is all the glitches are harmful?
A. All the glitches are not harmful.The glitches whose amplitude is more than VIL(low input voltage) then it will cause problem.
13. What is LEC check?
A. Optimized netlist must checked with final RTL netlist whether they are logically matched or not.
14. What are the types of wire load models?
A. a) Zero wire load model.
b) Standard wire load model.
c) Customized wire load model.
d) Auto wire load model.
15. Why we don't use HVT cells in lower technologies?
A. HVT cells responds to temperature inversion more effectively.so we don't use HVT cells.
16. What is physical knowledgeable synthesis?
A. After completion of floor plan and placement giving this information to logic synthesis is known as physical knowledgeable synthesis.
17. What is Steiner?
A. Routing the design with shortest path instead of H-V-H-V(horizontal vertical horizontal vertical) function(this is illegal ).
18. What is top-down methodology?
A. In this we need to synthesis entire RTL code of chip in a single slot.
19. What is black box?
A. In bottom-up approach if A&C block timing is closed but we are still working on B block then make B block as black box.
20. What is the tool used for Rc extraction?
A. Cadence :- QRC.
Synopsys :- Star RC.
21. What is the tool used for Signoff?
A. Cadence :- ETS.
Synopsys : Prime Time.
22. What is the tool used for Physical verification?
A. Cadence :- Assura.
Synopsys :- Hercules.
23. What is the tool used for Logical synthesis?
A. Cadence :- RTL compiler.
Synopsys :- Design compiler.
24. What is the tool used for Physical synthesis?
A. Cadence :- Encounter gps,pks.
Synopsys :- Physical compiler.
25. What is the tool used for PNR?
A. Cadence :- SOC encounter.
Synopsys :- IC compiler.
