PD interview questions and answers - part 3

by kamalnadh

1. What are the types of operating modes?
A. a) Test mode.
     b) Scan mode.
     c) Reset mode.
     d) Functional mode.

2. What is test mode and functional mode?
A. Test mode will detects manufacturing faults after fabrication and functional mode will detects faults at logic.

3.  What is Test clock?
A. If there is a separate clock for scan mode then that clock is known as Test clock.

4. What are the types of timing modes?
A. a) Single mode :- setup and hold check with a single library.
     b) Best case/Worst case mode :- setup with worst case mode and hold with best case mode.
     c) On chip variation mode :- setup and hold check with best case mode(lib1) and worst case mode(lib2)

 5. How can you know your netlist is good or bad?
A. If given netlist has buffering on clock and reset then it is not a good netlist.

 6. What is FIRE ICE?
A. Fast Interconnect Resistance Extractor Interconnect Capacitance Extractor(FIRE ICE) is a tool for RC extraction.

 7. What is Tap current?
A. It is the current drawn by the each and every transistor or standard cell.Based on width of standard cell we can calculate the current value this current is known as tap current.

 8. What is the manufacturing grid value?
A. It is the minimum value anything which is less than manufacturing grid value can't be read.

 9. Why we use layer map file?
A. It is used for interaction(mapping) between the QRC tech file and tech lef.QRC tech file and lef file contains different names for same metals to over come this problem we use layer map file.

 10. What is delay cell?
A. To fix hold tool will add cells in data path these cells are known as delay cells.It just produce output same as input with some delay.

 11. What is timing window?
A. Difference between early arrival time and late arrival time for each and every net is known as timing window.

 12. Is all the glitches are harmful?
A. All the glitches are not harmful.The glitches whose amplitude is more than VIL(low input voltage) then it will cause problem.

 13. What is LEC check?
A. Optimized netlist must checked with final RTL netlist whether  they are logically matched or not.

 14. What are the types of wire load models?
A. a) Zero wire load model.
     b) Standard wire load model.
     c) Customized wire load model.
     d) Auto wire load model.

 15. Why we don't use HVT cells in lower technologies?
A. HVT cells responds to temperature inversion more effectively.so we don't use HVT cells.

 16. What is physical knowledgeable synthesis?
A. After completion of floor plan and placement giving this information to logic synthesis is known as  physical knowledgeable synthesis.

 17. What is Steiner?
A. Routing the design with shortest path instead of H-V-H-V(horizontal vertical horizontal vertical) function(this is illegal ).

 18. What is top-down methodology?
A. In this we need to synthesis entire RTL code of chip in a single slot.

 19. What is black box?
A. In bottom-up approach if A&C block timing is closed but we are still working on B block then make B block as black box.

 20. What is the tool used for Rc extraction?
A. Cadence :- QRC.
     Synopsys :- Star RC.

 21. What is the tool used for Signoff?
A. Cadence :- ETS.
      Synopsys : Prime Time.

 22. What is the tool used for Physical verification?
A. Cadence :- Assura.
     Synopsys :- Hercules.

 23. What is the tool used for Logical synthesis?
A. Cadence :- RTL compiler.
     Synopsys :- Design compiler.

 24. What is the tool used for Physical synthesis?
A. Cadence :- Encounter gps,pks.
     Synopsys :- Physical compiler.

 25. What is the tool used for PNR?
A. Cadence :- SOC encounter.
     Synopsys :- IC compiler.


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ASIC design flow

by kamalnadh


               ASIC(Application specific integrated circuit) is designed for a special solo purpose and  the function of chip is same through out the chip life.It's digital circuitry is made up of permanently connected gates and flip flops in silicon so the logic function can't be changed.



specifications:-
             Day by day the technology is increasing and customer also expecting new features(like low power consumption,high speed) in the device.In this stage the features information which is expecting from the customer is collected by some marketing people.

Architecture design:-
             The architecture team will design an architecture based on the specifications.The architecture is like a block diagram we can find the all the details which are using in the design(like processors,memories) and how the are connected.This architecture team will estimate the block area,how much power is required and cost for the design.

RTL design:-
            Register transfer level(RTL) constructing a digital design using combinational and sequential circuit in hardware description language like verilog or VHDL.The above architecture is converted into verilog or VHDL code.This code describes how data is transformed as it is passed from register to register

 RTL verification:-
                It is a functional verification of RTL design.After the RTL design by applying test cases we verify the design in verification stage.If any mistakes are found then the design is re send to the RTL designing department.The verification stage will take nearly 60% of the total time.Performing this verification at this stage is most advantageous because correcting the faults at routing stage is difficult and takes more time.

 Synthesis:-
               It is a process of converting the RTL code into gate level netlist.Up to RTL verification the design is technology independent.In synthesys process the design is converted into technology dependent.it is 3 stage process.
1.Translation:- The RTL code is converted in to Boolean expression.
2.Optimization:- In this stage Boolean expression is optimized by SOP and POS optimization method.
3.Mapping:- In this technology independent Boolean expression is converted into technology dependent and generates the gate level net list.
The inputs for synthesis are RTL code, .SDC and .LIB.after the synthesis the generated outputs are gate level netlist and .SDC.

 DFT:-
         Design for testability(DFT) is a technique which facilitates a design to become testable after production.In this stage we put extra logic along with the design logic during implementation process which helps post production process.The DFT will make the testing easy at post production process.At this stage an ATPG(automatic test pattern generator) file will generated.

 Floorplan:-
              The floorplan is the process of determining the macro placement,power grid generation and i/o placement.It is the process of placing blocks/macros in the chip/core area there by determining routing areas between them.It determines the size of the die and creates wire tracks for placement of standard cells.It creates power straps and specifies pg connection.It also determine the i/o ,pin/pad placement information.

 Placement:-
          Placement is the process of automatically assigning correct position to standard cells on the chip with no overlapping.By global placement outside of standard cells will placed inside roughly.By the detailed placement the standard cells will place in site rows(legalize placement).In placement stage we check the congestion value by GRC map.
CTS (clock tree synthesis):-
               In this stage we built the clock tree by using inverters and buffers.In the chip clock signal is essential to the flip flops,to give the clock signal from clock source we built the clock tree.It is the process of balancing the clock skew and minimizing insertion delay in order to meet timing and power.
Routing:-
               Before the routing stage the connection between the macros,standard cells,clock,i/o port are logical connections.In this stage we connect all the cells physically with the metal straps.Routing is divided as two parts 1)global routing 2)detailed routing.The global routing will tell for which signal which metal layer is used.Before the detailed routing all are the logical connections.In detailed routing the physical connections are done.

Signoff:-

              After the routing the physical layout of chip is completed.In signoff stage all the tests are done to check the quality and performance of the layout before tapeout.After this the design is converted into GDS II file.

 Fabrication:-
                By the GDS II file  information we fabricate the chip.The total design is converted into chip by the manufacturing process.

 Packaging and testing:-
             After the fabrication process we test the chip.If there is any fault in the design then we modifies the design by repeating the steps.If there are no faults then chip will go to packaging. 
                              
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Physical Design MCQ questions


by kamalnadh
1) Threshold voltage depends on
     a) Temperature.
     b) Doping concentration.
     c) Oxide thickness.
     d) All.
2) Temperature inversion is
     a) Delay increase in higher technologies and decreases in lower technologies.
     b) Delay increase in lower technologies and decrease in higher technologies.
     c) Maintain the constant delay in high and low technologies.
     d) None.
3) Uncertainty is more in
     a) Hold.
     b) Setup.
     c) Both A&B.

4) If gate area is less than metal area then it leads to
     a) Antenna violations.
     b) Electromigration.
     c) Congestion.
     d) None.

5) Delay between shortest path and longest path in the clock is called......
     a) Global skew.
     b) Useful skew.
     c) Local skew.
     d) Slack.

6) HVT cell has
      a) Slower and more leakage power.
      b) Faster and more leakage power.
      c) Slower and less leakage power.
      d) Faster and less leakage power.

 7) FRAM view has
       a) Layout information and used at the time of tape-out.
       b) Layout information and used in place&route.
       c) Abstract view and used in place and route.
       d) Abstract view and used at the time of tape-out.

 8) Clock gating is used to reduce
      a) Static power dissipation.
      b) Dynamic power dissipation.
      c) Short circuit current.

 9) Tap cells are used
       a) To avoid the dynamic IR drop.
       b) To connect the gap between cells.
       c) To avoid dynamic power dissipation.
       d) To avoid latch up problem.

10) HFNS is used
       a) To balance the timing.
       b) To balance the power.
       c) To balance the load.
       d) None.

11) To detect manufacturing faults in macros we use
       a) JTAG (joint test action group).
       b) MBIST (macro built in self test).
       c) LVS.
       d) All.

 12) Cross-talk can be avoided by...
       a) Using low metal layers.
       b) Using long nets.
       c) Decreasing the spacing between the metal layers.
       d) Shielding the nets.

13) CRPR stands for...
       a) Clock reconvergence past removal.
       b) Cell reconvergence pessimism removal.
       c) Clock reconvergence pessimism removal.
       d) Clock reconvergence present removal.

 14) what are the pre routing in the design
        a) Signal routing.
        b) Power routing.
        c) Signal and power routing.
        d) None.

 15) Which configuration is more preferred during floor planning
         a) With channel spacing between rows and no double back.
         b) Double back with non flipped rows.
         c) With channel spacing between rows and no double back.
         d) Double back with flipped rows.

 16) Which gate is most preferred in the design
         a) NOR.
         b) NAND.
         c) AND.
         d) XOR.

 17) Elecromigration can be reduced by
        a) Increasing the width.
        b) Increasing the spacing between nets.
        c) Both A&B.
        d) Blockages.

 18) I/O delays are more than cell delay
        a) True.
        b) False.
 19) Major importance of power plan is
        a) IR drop.
        b) Electromigration.
        c) Congestion.
        d) Both A&B.

   20) End cap cell is used
        a) To avoid the dynamic IR drop.
        b) To avoid cell damage at the end of row.
        c) To avoid dynamic power dissipation.
        d) To connect the gap between cells.

   21) HFNS is used at the stage of
         a)CTS.
         b) Placement.
         c) Routing.
         d) Floor plan.

 22) Virtual clock is
         a) Logically not connected.
         b) Physically doe't exist.
         c) Both a&b.
         d) None.

 23) Which of the following metal layer has max resistance
        a) Metal 3.
        b) Metal 5.
        c) Metal 2.
        d) Metal 6.

 24) Chip utilization depends on..........
         a) Only standard cells.
         b) Standard cells and macros.
         c) Only macros.
         d) Standard cells,macros,I/0 pads.

  25) To achieve better timing.......cell are placed in critical path
          a) HVT
          b) LVT
          c) SVT

  26) Delay of cell depends on____
         a) Input transition and output load.
         b) Output transition and input load.
         c) Output transition and output load.
         d) Input load and output transition.

  27) Clock tree does't contain following cell....
          a) Clock buffer.
          b) AOI cell.
          c) Clock inverter.
          d) None.

 28) What is the effect of high drive strength buffer when added in long net
         a) Delay on net decreases.
         b) Capacitance on net increases.
         c) Delay on net increases.
         d) Distance on the net increases.

  29) LVT cell has
        a) Faster and more leakage power.
        b) Slower and more leakage power.
        c)  Faster and less leakage power.
        d) Slower and less leakage power.

  30) Cell view has
          a) Layout information and used at the time of tape out.
          b) Abstract view and used in place and route.
          c) Layout information and used in place&route.
          d) Abstract view and used at the time of tape out.

   31) Jitter is the
          a) Difference between two clock pulses.
          b) Ratio of input transition and output load.
          c) Deviation of clock edge from its ideal position.
          d) Difference between required time-arrival time.

   32) Decap cell is used
           a) To avoid the dynamic IR drop.
           b) To avoid cell damage at the end of row.
           c) To avoid dynamic power dissipation.
           d) To connect the gap between cells.

   33) Hard macro is
           a) Circuit is fixed,we know only timing information and don't know the functional information.
           b) Circuit is not fixed,we know the timing and functional information.
           c) Circuit is fixed,we don't know the timing and functional information.
           d) Circuit is fixed,we know the timing and functional information.

   34) Which design is more complicated
          a) 500mhz.
          b) 54mhz.
          c) 500khz.
          d) 650mhz.

    35) Clock skew can be minimized by
           a) Buffering the clock.
           b) Add delay in data path.
           c) Clock reversing.
           d) A&C.
           e) A,B&C.

   36) FPGA chip is
          a) Simple in design.
          b) It can be re programmed.
          c) Manufacturing time is less.
          d) A&C.
          e) A,B&C.


   37) Capacitance table can be created by
          a) .tf file
          b) .lib file
          c) lef file
          d) .sdc

    38) To detect manufacturing faults in I/O we use
            a) JTAG (joint test action group).
            b) MBIST (macro built in self test).
            c) LVS
            d) All

    39) ASIC chip is
            a) Simple in design.
            b) Manufacturing time is less.
            c) It is faster.
            d) Both A&C.

    40) Use of placement blockage is 
            a) Block the cells in specific area.
            b) Reduce the congestion.
            c) Defines std cell area.
            d) A&B.
            e) A,B&C.

    41) In soft blockage........cells are placed
             a) No cells.
             b) Only buffers and inverters.
             c) Only sequential cells.
             d) Any cells.

     42) More IR drop due to...
             a) Increase in metal width.
             b) Decrease in metal length.
             c) Lot of metal layers.
             d) Increase in metal length.

    43) To avoid cross-talk the shielding net is usually connected to____
           a) VDD.
           b) clock.
           c) VDD and VSS.
           d) VSS.

   44) Which of the following is preferred while placing macros
          a) Macros placed left and right side of die.
          b) Macros placed center of the die.
          c) Macros placed top and bottom side of die.
          d) Macros placed based on the connectivity of the I/O.

   45) Pitch of the wire is______
           a) Min width.
           b) Min width+min spacing.
           c) Min spacing.
           d) Min width-min spacing.


   46) In 9 metal layer design which metal layer you will use for power
          a) Metal 5 and metal 6.
          b) Metal 6 and metal 7.
          c) Metal 8 and metal 9.
          d) Metal 4 and metal 5.

   47) After the final routing the violations in the design
           a) There can be hold violations but not setup violations.
           b) There can be both violations.
           c) There can be setup violations but not hold violations.
           d) There can be no setup and no hold violations.

    48) JTAG cell is used
           a) To check the io connectivity.
           b) To avoid cell damage at the end of row.
           c) To avoid dynamic power dissipation.
           d) To connect the gap between cells.

    49) Soft macro is
            a) Circuit is fixed,we know only timing information and don't know the functional information.
           b) Circuit is not fixed,we know the timing and functional information.
           c) Circuit is fixed,we don't know the timing and functional information.
           d) Circuit is fixed,we know the timing and functional information.

    50) Latch-up problem can be reduced by
            a) Increasing the spacing. 
            b) Increase the doping concentration.
            c) Use of guard rings.
            d) All 

    51) Antenna problem can be caused by
            a) Increasing the net length.
            b) Decreasing the net length.
            c) Increasing the load.
            d) None.

   52) Cross-talk can be reduced by
           a) Increasing the spacing between nets.
           b) Shielding.
           c) Decreasing the spacing between nets.
           d) Both A&B.

   53) FPGA stands for
           a) Field programmable gate array.
           b) Fixed programmable gate arrangement.
           c) Fixed programmable gate array.
           d) None

   54) Pre-routing means routing of.....
           a) Clock nets.
           b) Signal nets.
           c) IO nets.
           d) PG nets.

    55) Hold is fixed....
           a) Before CTS.
           b) Before placement.
           c) After CTS.
           d) After placement.

    56) Which of the following is best suited for CTS
         a) Buffer.
         b) Clk buffer.
         c) Inverter.
         d) Clk inverter.

    57) Routing congestion is___
          a) Available tracks are less than required tracks. 
          b) Depends on the routing layers available.
          c) Required tracks are less than available tracks.
          d) None.

    58) Halo allows the placement of
          a) Only standard cells.
          b) Only macros.
          c) Only buffers and inverters.
          d) None.

    59) Aspect ratio is
         a) Width /height.
         b) Height/width.
         c) Width+height.
         d) Width -height.

    60) What is the goal of CTS
           a) Minimum EM.
           b) Minimum slack.
           c) Minimum skew.
           d) Minimum IR drop.

   61) If arrival time is more than required time______violations will come
            a) Setup.
            b) Hold.
            c) Both.
            d) None.

   62) Maximum voltage drop will be there at(without macros)......
          a) Right and left side.
          b) Middle.
          c) Top and bottom side.
          d) None.

    63) The solution of antenna effect is.....
           a) Shielding.
           b) Buffer insertion.
           c) Diode insertion.
          d) Double spacing.

     64) Which of the following is not present in SDC file
            a) Max transition.
            b) Max current density.
            c) Max capacitance.
            d) Max fan out.

     65) Which is the following is not present in logical DRC's
          a) Max transition.
          b) Shorts.
          c) Max fan-out.

     66) Congestion can be reduced by
           a) Adjusting the cell density in congested area.
           b) Using proper blockage.
           c) Both A&B.
           d) None.

     67) The metal area and(or)perimeter of conducting                       layer/gate to gate area is called...
            a) Aspect ratio.
            b) OCV.
            c) Antenna ratio.
            d) Utilization.

     68) search and repair is used for.....
           a) Reduce EM violations.
           b) Reduce IR drop.
           c) Reduce DRC.
           d) None.

      69) Maximum current density of metal is available in....
             a) .lib
             b) .tf
             c) .lef
             d) .sdc


     70) Dynamic power consumption can be reduced by
             a) Reduce voltage swing in all nodes.
             b) Reduce the load capacitance.
             c) Both A&B. 
             d) None.

     71) what violations solved in LVS
             a) Shorts.
             b) Opens.
             c) Missing text layers. 
             d) All.

     72) Utilization of chip after placement optimization will be_
            a) Decreases.
            b) Constant.
            c) Increases.
            d) None.

     73) Routing congestion can be avoided by.......
           a) Distributing cells.
           b) Placing cells closer.
           c) Placing cells at corners.
           d) None.

     74) No.of tracks in high metal layer will be..... tracks in low metal layer   
           a)  Less than.
           b) More than.
           c) Equal to.

 75. Which is not preferred for clock buffers 
       a) SVT.
       b) LVT.
       c) HVT.
       d) None

 76. Placement blockage is created at the stage of floor plan  
      a) True
      b) False

 77. Abutted design has 
      a) No gap between blocks.
      b) Gap between the blocks.
      c) Both A&B.
      d) None

 78. In power planning stage rings are placed 
      a) In middle of core.
      b) Around the core.
      c) At corner.
      d) None

 79. Scan chain re ordering will reduce congestion 
     a) True
     b) False

 80. Static power can be reduced by placing  
      a) LVT cells
      b) SVT cells
      c) HVT cells

 81. Dynamic power consumption can be reduced by 
     a) Load capacitance.
     b) Cell sizing.
     c) Load sharing.
     d) All of the above.

 82. CTO can be performed by 
     a) Buffering.
     b) Gate sizing.
     c) Both A&B.
     d) None


Answers:- 


1) D
2) A
3) B
4) A
5) A
6) C
7) C
8) B
9) D
10) C
11) B
12) D
13) C
14) B
15) D
16) B
17) A
18) A
19) D
20) B
21) B
22) C
23) C
24) B
25) B
26) A
27) B
28) A
29) A
30) A
31) C
32) A
33) A
34) D
35) E
36) E
37) C
38) A
39) C
40) C
41) B
42) D
43) D
44) D
45) B
46) C
47) B
48) A
49) B
50) D
51) A
52) D
53) A
54) D
55) C
56) B
57) A
58) C
59) B
60) C
61) A
62) B
63) C
64) B
65) B
66) C
67) C
68) C
69) B
70) C
71) D
72) C
73) A
74) A
75) C
76) A
77) A
78) B
79) A
80) C
81) D
82) C
83)
84)
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