PD interview questions and answers -part 2

by kamalnadh

Q 1.What are the types in physical verification?
 A. LVS (layout vs schematic).
      DRC (design rule constrain check).
      ERC (electric rule check).
      LEC (logical equivalence check).

Q 2.How to fix setup and hold violations at a time?
A. It is not possible to fix both at a time because if we increase the delay in data path it's good for hold and bad for setup.But there is only one way to fix it.

• Buffer the data path for hold fix.
• Slow the clock frequency for setup fix (this is not a valid fix,but we don't have other option).

Q 3.How can you avoid cross-talk?
A. a) Increase the spacing between the aggressor and victim nets.
     b) Shielding.
     c) Maintain the stable supply.
     d) Increase the drive strength of cell.
     e) Layer jumping.
     f) Victim net width increasing then resistance decreases.
     g) Guard ring.
     h) Cell sizing (up sizing).


Q 4.What is cross-talk?

A. It is the undesirable electric interaction between two or more physical adjust nets due to the capacitance cross coupling.When two nets are in parallel the electric field of one net is effects the other net which is nearer to it.This called cross-talk effect. 

Q 5.What is scan chain reordering?

A. It is the process of re connecting the scan chains in the design to optimize for routing by reordering the scan chain connection which improves timing and congestion.

Q 6.What is the concept of rows in the floor plan?
A. The std-cells in the design are placed in rows.All rows have equal height and spacing.The width of the row can vary.The std-cell in the row get the power and ground connection from vdd and vss rails.Sometimes technology allows the rows to be flip.So they can share the power  and ground rails in vdd-vss-vdd patron.


Q 7.What are the advantages of NDR's?
A. a) By applying the double width we can avoid the EM.
     b) By applying double spacing we can avoid the cross-talk.
     c) Help's to avoid congestion at lower metal layer.
     d) Help's pin accessibility of std-cells .

Q 8.What is temperature inversion?
 A. At higher CMOS technologies cell delay increases when temperature increases.But when you are in lower technologies i.e below 65nm cell delay has inversely proportional to temperature.

Q 9.In reg to reg path if you have setup problem where will you insert buffer?
A. We can insert buffer near to launch flop which decreases the transition time.Hence decreasing the wire delay therefore overall delay will decrease.When arrival time will decrease setup violations will reduce(required time-arrival time).

Q 10.What is partitioning?
A. It is the process of dividing the chip into small blocks this is done mainly to separate different functional blocks and also make placement.routing easier.

Q 11.How can you reduce dynamic power?
A. a) Reduce power supply voltage.
     b) Reduce voltage swing in all nodes.
     c) Reduce the switching probability (transition factor).
     d) Reduce load capacitance.

Q 12. Why double via insertion?
A. To reduce the yield loss due to via failures,double via's are inserted traditionally double via's where inserted in post route and then modify the routing to fix any DRC's.

Q 13.What is metal fill insertion?
A. At the time of etching they use some type of chemicals due to that chemical metal loss will be more for that reaction we are inserting the metal fills.

Q 14.What is metal slotting?
A. It is the Technic for avoiding the problems like metal lift off and metal erosion.

Q 15.What are the power dissipation components?
A. Dynamic power consumption:- Occurs when signals which go through the CMOS circuit change there logic state by charging discharging of o/p node capacitor.
static (leakage power consumption):- It is the power consumed by the sub threshold currents and by reverse biased diodes in a CMOS transistor.
short circuit power consumption:- It occurs during switching on both the NMOS and PMOS transistors in the circuit and they conduct simultaneously for a short amount of time.

Q 16.What is dishing effect?
A. It is defined as the difference between the height of the oxide in the spaces and that of the metal in the trenches.It is caused by CMP.It may reduced by some dummy fill Technics effectively.

Q 17.What is CMP (chemical mechanical polishing)?
A. It is the process of smoothing surface with the combination of chemical and mechanical forces.It is used in IC fabrication to get a high level of polarization.

Q 18.What is the use of placement blockage?
A. a) Defines std-cell and macro area.
     b) Reserve channels for buffer insertion.
     c) Prevent cells from being placed at or near macros.
     d) Prevent congestion near macros.

Q 19.What are the types of global routing?
A. a) Time driven global routing.
     b) Cross-talk driven global routing.
     c) Incremental global routing.

Q 20.What are the violations solved in LVS?
A. a) Shorts.
     b) Opens.
     c) Missing text layers.
     d) Missing lib in GDS.
     e) Missing soft layers.

Q 21.What is the clock latency?
A.It is the delay between the clock source and clock pin.It is two types.Clock source latency and clock network latency.The time taken from clock source to definition pin is the clock source latency and from the clock definition pin to clock pin of the flip flop 2 is the clock network latency.

Q 22.How to fix setup and hold violations?
A. Setup:-

• Reduce the amount of buffers in the path.
• Replace buffers with 2 inverters.
• Replace HVT cells with LVT cells.
• Increase the drive size/strength.
• Insert repeaters.
• Adjust cell position in layout.

     Hold:-

• By adding delay in data path.
• Decrease the drive strength in data path.

Q 23.What are the inputs of floor plan?

A.

• .v
• .lib and .lef
• .sdc
•  tlu+ file
•  Physical partitioning information of design.
•  Floor plan parameters like height,width,aspect ratio,utilization.
•  Pin/pad position.

Q 24.What are the outputs of floor plan?
A. 

• Die/block area.
•  I/O pad placed.
•  Macro placed.
•  Power grid design.
•  Power pre routing.
•  Std-cell placement area.

Q 25.What is keep-out margin?
A. It is the region around the boundary of fixed macros in design in which no other macros or standard cells not allows.It allows only buffers and inverters in it's area.

Q 26.How will you synthesize clock tree?
A.a) Single clock-normal synthesis and optimization.
    b) Multiple clocks-synthesis each clock separately.
    c) Multiple clocks with domine crossing synthesis each clock                separately and balance the skew.

Q 27.What is IR drop?
A. Each metal layer has a resistance value.When the current flows through the metal the resistance consumes some current.This is the IR drop.If the resistance is more the drop also more.

Q 28.how to reduce power dissipation using HVT and LVT in the design?
A.If we have positive slack use HVT cells in the path and use LVT cells in the path when we have negative slack.HVT cells have large delay and less leakage power. LVT cells have less delay and      more leakage power.To meet the timing use LVT cells and to reduce the leakage power use HVT cells.


Q 29.What is wire load model (WLM)?
A. It is an estimation of delay based on area and fan-out.The delay depend on..
     Resistance.
     Capacitance.
     Area of the nets.

Q 30.What is signal integrity?
A. It is the ability of an electric signal to carry information reliably and to resist the effects (cross-talk, EM) of high frequency electromagnetic interface from near by signals.

Q 31.Doe's cross-talk always cause violations?
A.Yes it is because cross-talk adds or subtracts energy to the signal which cause setup or hold violations.

Q 32.How a positive or negative edge triggered flip flop will effect the setup and hold violations?
A. Positive edge triggered flip flop will favour to setup (setup violations will reduce).Negative edge triggered flip flop will favour to hold (hold violations will reduce).

Q 33.What are the i/p's and o/p's of power planing?
A. i/p's:-

• Data base with valid floor plan.
• Power rings and power straps width.
• Spacing between vdd and vss straps.

     o/p:-

• Design with power structure.

Q 34.What are the i/p's and o/p's of placement?
A. I/P's:-

• Netlist.
• Mapped and floor planed design.
• Logical and physical lib.
• Design constraints.

    O/P 's:-

• Physical layout information.
• Cell placement location.
• Physical layout,timing and technical information of lib.

Q 35.If we increase the fan-out of the cell how it will effects delay?
A. Fan-out lead to increased capacitive load on the driving gate.Therefore longer propagation delay.

Q 36.What is multi driven nets?
A. It can be created in RTL by introducing drivers of same or different signal strengths.However during a net with multiple signals are not considered as a good practice.This could lead to failure in a post silicon verification as the driver strength can potentially get heavily altered during manufacturing defects.Many EDA tools don't allow multi driven nets in the design and the designers are expected to remove all multi driven nets from the design.

Q 37.What is magnetic placement?
A. To improve the timing for the design or to improve the congestion for a complex floor plan we can use magnetic placement to specify fixed objects as magnets and icc moves their connected standard cells close to them.For the best results perform the magnetic placement before standard cells are placed.

Q 38.What is lookup table?
A.The table is drawn by using input transition and output load values.It is used to calculate the cell delay.

Q 39.What does we do for low power design?
A. We apply low power techniques

• Clock gating.
• Multi voltage design.
• Power gating.
• Multiple vt libraries.

Q 40.What are the types of checks done in prime time?
A. a) Timing (setup,hold,transition).
     b) Design constraints.
     c) Nets.
     d) Noise.
     e) Clock skew.

Q 41.What analysis we do during floor plan?
A.a) Overlapping of macros.
     b) Allowable IR drop.
     c) Global route congestion.
     d) Physical information of the design.

Q 42. What are the different types of delay models?
A. a) WLM (wire load model)
     b) NLDM ( non linear delay model)
     c) CCS (composite current source)

Q 43.Where placement blockage is created?
A. At floor plan stage it acts like guidelines for placement of standard cells.In CTS stage in order to balance the skew more  no.of buffers and inverters are added and blockages are used to reserve space for buffer and inverter.

Q 44.Why we apply NDR's in placement?
A. Applying NDR's in placement because of avoiding congestion and timing problem.These problems are difficult to fix at routing.These are special rules like double spacing and double width.

Q 45.What is mesh?
A. The horizontal and vertical power straps in the design are called mesh.

Q 46.Why I/O cells are placed in the design?
A. The i/o cells are the one which interact in between the blocks outside of the chip to internal blocks of the chip.In floor plan stage i/o cells are placed in between core and die.These are responsible for providing voltage to the cell in the core.

Q 47.What are the complex cells in the floor plan?
A.These are the cells which are made of group of std-cells based on functionality requirement.This cells height is grater than the std-cells and lesser than the macros.

Q 48.How to fix Electromigration (EM)?
A. a) Down size the driver.
     b) Increase the metal width.
     c) Add more vias.
     d) Spread cells.

Q 49.What is etching?
A.It is used in micro-fabrication to chemically remove layers from the surface of the wafer during manufacturing.

Q 50.What is SOI technology?
A.It refers to use of layered silicon insulator.It reduces leakage current and lower power consumption.

Q 51.What is aggressor and victim?
A.these two terms will come in cross-talk concept.
    Aggressor:- A net which create the effect on nearer net(victim).
    victim:- A net which receives the effect from nearer net(aggressor).

Q 52. What is Mealy and Moore?
A. Mealy:- The outputs are depends on input and present state.
     Moore:- The outputs are depends on only present state.


     

  

STA

by kamalnadh


STA:-
         It is a method to determine if the circuit meets timing constraints without simulation.It provides faster and simple way of checking and analyzing all the timing paths in the design for any timing violations.

  Advantages:-

•  Speed.
•  Exhaustive timing coverage.
•  Capacity to handle full chip. 
•  Vector simulation is not required.

Disadvantages:-

•  It can report false errors.
•  It is pessimistic.
•  It is not suitable for asynchronous circuits.
•  It can't detect errors related to logical operation.

Inputs of STA:-

•   Netlist
•  .lib
•   Spef file
•  .SDC(consrtaints)

Setup:-
         It is the The minimum time required for the data to be stable before the clock edge.

                                                  Fig:- Setup

Explanation:-

            Here we are considering two flip flops with same clock pulse.In above fig ff 1 sows the clock pulse of flip flop 1 and ff 2 shows the clock pulse of flip flop 2.For setup we should consider data path.The data is launched at ff 1 and captured at ff 2. The data is launched at rising edge of ff 1 and it should be captured before the next rising edge of the ff 2 clock.If the data is captured before the next rising edge then the time is beneficial.If the data is captured after the next rising edge then violations will occur these are called setup violations.

                  In simple words the data should capture with in full cycle.

                     

                   Setup slack = Required time – Arrival time 

Hold:-

                

          The minimum time required for the data to be stable after the clock edge.    

                                            Fig:- Hold

Explanation:-

                         Here we are considering two flip flops with same clock pulse.In above fig ff 1 sows the clock pulse of flip flop 1.and ff 2 shows the clock pulse of flip flop 2.For hold we are considering clock path.Here the data is launched and captured at the same edge.If the data is captured after the clock edge of the ff 2 then the time is benefited.If the data is captured before the clock edge of the ff 2 then violations will occur.These are called hold violations.

               In simple words the data should launch and capture at the same edge of the clocks.

                           Hold slack = Arrival time – Required time

Data paths in STA:-

      1.Input port to register

      2.Register to register

      3.Register to output

      4.Input port to output port

Timing constraints:-

1.False path:- It specifies the logic path.In below fig when enable is 0 the output is 8( from first block 5  is active and from second block 3 is active 5+3=8) if we did't specifies the logic path tool will take wrong path like (5+5 or 3+3).

2. Multi cycle path:- It specifies the no of clock cycles required to propagate data from start to end of the path.

In above fig 2 cycles are used to propagate the data.

3.Min/Max delay:- It over ride the default setup and hold constraints with specific max and min time values

Latency (or) clock network delay (or) insertion delay:-

               It is the time taken by the clock to reach the clock pin from the clock source.It is divided in to two types.Clock source latency and clock network latency.

           Here from clock source to definition pin is the clock source latency.From the clock definition pin to clock pin of the flip flop 2 is the clock network latency.

Cell delay (or) propagation delay:-

         cell delay is the amount of delay from input to output of of a logic gate in a path.

Net delay:-

          It is the amount of the delay fro the output of cell to the input of next cell in the timing path.It is caused by the parasitic capacitance of the interconnection between two cells,combined with the net resistance and the limited drive strength of driving cell.

Drive strength:-

           It is the capacity of the cell to drive a value to the cell connected to it's output.Small stranded cell have small capacitance and vice versa.It is easier to drive a small cell than large.

Transition delay (or) slope (or) wave delay (or) slew:-

            Time taken to a signal to reach from 10% of vdd to 90% of vdd is called transition delay. 

Clock uncertainty:-

           It is the deviation of the actual arrival time of the clock edge with respect to ideal arrival time.The deviation happens mainly due to the jitter and noise.

In the fig above clock is normal.below clock is deviation of arrival time from it's ideal position.

Clock gating:-

       It is the popular Technic used in many synchronous circuits foe reducing dynamic power dissipation.It saves power by adding more logic to a circuit to prune the clock tree.

OCV (on chip variation):-
          
         The delay values of IC will varies in different conditions like changing in processor,voltage,temperature(PVT).The delay value of IC in cold weather is different and in hot weather is different.In cold weather the metals in ic will shrink.In hot weather the metal will expand so the delay will increase.To over come this effect flat derate(delay)  is applied in the circuit.
                    In simple words OCV is a technique in this flat derate is applied to make faster path more fast and slower path more slow.Delays varies across a single die due to PVT(processor,voltage,temperature) .This need to be modeled by scaling the coefficients.


CRPR (clock re convergence pessimism removal):-   

            In this concept we removes the pessimism and derate to the common path.Generally we add the delay to every buffer in the process of OCV.But adding more delay is also effect the speed of the chip and it may cause violations to over come this we are removing the delay to the common path in the process of CRPR.
               In simple words  It can be used to remove the pessimism and penalty by using common cell for both launch and capture flip flop.

Derating:-

           Timing derating factors models the effects of varying operating conditions by adjusting the delay values calculated for the individual timing arc of a block.

PVT operating conditions:-

          PVT is to model inter chip variations. OCV is to model intra chip variations.

Process:- If the processor length is increases the delay also increases

Voltage:- If voltage is increases delay will reduces.

Temperature:-If temperature increases delay will increases.

Libraries in STA:-

1.Link lib:- It provides reference path

2.Target lib:-It is used for optimization

3.Symbolic lib:-It having symbols of cells(gates)
4.synthetic lib:- AOI and OAI combinations.

5.Design ware lib:-Provides the connectivity port.

6.physical lib:-It have shape of cells.

Skew:-

    Difference between the two clock network delays is called skew.types of skews are given below.

Useful skew:-If the clock skew is intentionally added to meet the timing or reduce the violations this is called useful skew.

Local skew:-It is the difference in the arrival of clock signal at the clock pin of related flip flops.
Global skew:-It is the difference in the arrival of clock signal at the clock pin of non-related flip flops.

Some definitions:-

Jitter:- Deviation of clock edge from it's ideal position.

Arrival time:-It is the time required for data travel through the      data path.

Required time:-It is the time required for clock travel through        the clock path.

Recovery time:- It is the minimum time that an asynchronous control i/p pin must be stable after being deserted and before the next clock transition.

Removal time:- It is the minimum time that an asynchronous control input pin must be stable before being deserted and after the previous clock transition.