Physical design flow

by kamalnadh


PD flow:-

Physical design:-  It is the process of transforming a circuit description into physical layout.which describes the position of cells and routes for the interconnection between them.the physical design process stages are listed below.

Import design:-

           It is the first stage in physical design.In synthesis process the RTL code is converted into netlist.In this import design stage all input files are read by the tool.By using this information the design process will starts.

Floorplan:-
            The floorplan is the process of determining the macro placement,power grid generation and i/o placement.It is the process of placing blocks/macros in the chip/core area there by determining routing areas between them.It determines the size of the die and creates wire tracks for placement of standard cells.It creates power straps and specifies pg connection.It also determine the i/o ,pin/pad placement information.

                      

Placement:-
          Placement is the process of automatically assigning correct position to standard cells on the chip with no overlapping.By global placement outside of standard cells will placed inside roughly.By the detailed placement the standard cells will place in site rows(legalize placement).In placement stage we check the congestion value by GRC map.

(Note:- For just understanding purpose standard cell size was increased.in practical standard cell and rows are too small compare to macros.Count of std cells also high.ex:-50k)

CTS(clock tree synthesis):-
               In this stage we built the clock tree by using inverters and buffers.In the chip clock signal is essential to the flip flops,to give the clock signal from clock source we built the clock tree.It is the process of balancing the clock skew and minimizing insertion delay in order to meet timing and power.

Routing:-

               Before the routing stage the connection between the macros,standard cells,clock,i/o port are logical connections.In this stage we connect all the cells physically with the metal straps.Routing is divided as two parts 1)global routing 2)detailed routing.The global routing will tell for which signal which metal layer is used.Before the detailed routing all are the logical connections.In detailed routing the physical connections are done.

Signoff:-
              After the routing the physical layout of chip is completed.In signoff stage all the tests are done to check the quality and performance of the layout before tapeout.

Floorplan

by kamalnadh

                                 Floorplan

                    It is the first stage in the physical design.The quality of floorplan will decide the total chip performance.The floorplan is the process of determining the macro placement,power grid generation and i/o (or) pin placement.
            It is the process of placing blocks/macros in the chip/core area there by determining routing areas between them.It determines the size of the die and creates wire tracks for placement of standard cells.It creates power straps and specifies pg connection.It also determine the i/o,pin/pad placement information.

  Before discussing about floorplan let see few definitions in floor plan.
Macro:- These are special memory elements used to store the data efficiently and also don't occupy much space on the chip comparatively these memory cells are called macros.All memories are macros but all macros are not memories.

Hard macro:- The circuit is fixed and we don't know which type of gates using inside.We know only timing information not the functional information.

Soft macro:- The circuit is not fixed and we know which type of gates using inside.We know timing information and also functional information.

Core:- It is defined as the inner block which contains the std cells and macro.

Die:- It is the block around the core which contain i/o ports.

Halo:- It is the region around the boundary of fixed macros in design in which no other macros or standard cells can be place.If macros moves halo will also move.


Blockage:- It can be specified for any part of the design.If we move the block blockage will not move.

Placement blockage:- It prevents the tool from placing the cells at specific region.

Types of floorplan techniques used in full chip plan:-

  1.Abutted:- When the chip is divided into blocks in abutted design there is no gap between the blocks.

  2.Non abutted:- In this design there is a gap between blocks.The connection between the blocks are done through the routing nets.

  3.Mix of both:- This design is combination of abutted and non- abutted. 

Input files of floorplan:-

•    .v (netlist)
•   .sdc (synthetic design constraints)
•   .lib (logical libraries)
•   .lef (physical libraries)
•   .tf (technology file)
•   .tlu+
•   .tdf

  Steps in floorplan:-

• Giving aspect ratio:- Aspect ratio will decides the size and shape of the chip.It is the ratio between vertical routing resources to horizontal routing resources (or) ratio of height and width.If aspect ratio is 1 that means height and width of the chip is same.If aspect ratio is 0.5 that means width is 2 times of height (height=1,width=2).

                Aspect ratio = Height/width

• Core utilization:- Utilization will defines the area occupied by the standard cells,macros and other cells.If core utilization is 0.7 (70%) that means 70% of core area is use for placing the standard cells,macros and other cell and remaining 30% is used for routing.

         

• Placing macros inside core:- The main step in floorplan is placing the macros inside the core.After giving of aspect ratio and utilization factor chip size and shape was created.All the stranded cells and macros are placed outer side of the chip.In this floor plan stage we have to place the macros by some guide lines like fly line analysis,port communication,macro grouping etc.

            

• Cut the rows on macros:- In floor plan stage rows are created inside the core to place the standard cells.When we place macros inside the chip the rows will over laps the macros.so we need to cut the rows on macros.

• insert physical cells:- Inserting physical cells like tap cells,end cap cells,filler cells etc.These cells will protect the chip from faults. 

• i/o placement:- I/O pads are placed at the boundaries.In block level these i/o pins are placed at input and output side of the block to interact with other blocks and transfer the signals.After that logical cell placement blockage is created in die area to prevent the logical cell placement.The die area is only for the i/o pins.

• creating blockage:- Placement blockage is applied in the floor plan stage to prevent standard cell placement.If we don't apply the placement blockage there is a chance to overlap the standard cells on macros.We applied this at macros area so there is no chance to overlap the standard cells on macros.

Guide lines for macro placement:-

• Flyline analysis.
• Port communication.
• Macro grouping. 
• Spacing between macros.
• Macros placed at boundaries.
• Macro alignment.
• Blockages.
• Avoiding crisscross connections of macros.

Outputs of floorplan:-

• Macro placed.
• Power grid design.
• I/O placed.
• Standard cell placement area.
• Block area.

                                                                Power planning
             
Inputs of power plan:-

• Database with valid floor plan
• Power rings and power straps width
• Spacing between VDD and VSS straps

Few definitions in the power plan:-
Mesh:- Horizontal and vertical power straps in the design are called mesh.

Straps:- Strap is a net(metal layers) which carry the power.

IR drop:- Each metal layer has a resistance value.when the current flows through the metal the resistance consumes some current.This is the IR drop.If the resistance is more the drop also more.

Electromigration(EM):- When high current density continuously flows through a metal due to the high current the atoms moving with kinetic energy and they transfer the energy to another atoms and increases the temperature due to these the metal will damage.

Via:- It is a electrical interaction between the two metal layers.

power planing:-
               Power planing is used to equally distribute the power to the cells (macros,standard cells and other cells) in the chip.Normal power connection will not the distribute the power equally throughout the chip so we choose special power design to chip to carry power throughout the chip equally.In this step there are three levels of power distribution

• Rings
• Straps
• Rails

Rings:- Ring is placed around the chip which carries VDD and VSS
Straps:- It is difficult to transfer the power equally from edge of the chip to center of the chip.so we so we placed horizontal and vertical nets(metal layers) in the chip from the rings to carry the power.
Rails:- This rail will connect the VDD and VSS to Std cells.

In the above fig VDD and VSS are the straps.

  In power planning we mainly concentrates on IR drop and Electromigration. In power planing power is mostly transferring through the power straps.So we have to decrease the IR drop.IR drop is caused by the resistance if the resistance is more then the IR drop also more.Top meta layers will have less resistance so IR drop will decreases so we choose top metal layers.
      How to decrease IR drop:-

•  Adding more straps
•  Increase strap width

Electromigration is leads to damage the metal.When high current flows through the metal layer the atoms in the metal also moves and the temperature will increases which cause the metal damage.so we have to reduce this effect.
        How to fix Electromigration:-
           a) Down size the driver.
          b) Increase the metal width.
          c) Add more vias.
          d) Spread cells.

Outputs of power planning:-

• Design with power structure

                   

     

Placement

by kamalnadh

                              Placement
                            
                   Placement is the process of automatically assigning correct position to standard cells on the chip with no overlapping. By global placement outside of standard cells will placed inside roughly.By the detailed placement the standard cells will place in site rows(legalize placement).In placement stage we check the congestion value by GRC map.

Inputs of placement:-

•  Floorplan design.
•  Netlist.
•  Design constraints.
•  Logical library(.lib),physical library(.lef).

Before discussing about placement let see few definitions in placement.

Blockage:- Blocking a specific are to prevent placing of cells.

Hard blockage:- It does't allow inverters,buffers,standard cells.

Soft blockage:- It allows only inverters and buffers and blocks standard cells.

Partial blockage:- It will allow both buffers and standard cell in a percentage value.

Congestion:- when the available tracks are less than the required tracks this effect will occur.When the signals are more than the tracks then congestion will occur.

HFNS (high fan-out net synthesis ):- HFNS is the process of buffering the high fan-out nets to balance the load.

Scan chain:- It is used in design for testing.It makes testing easier by setting a group of Flip-flops connecting serially.

Goals of placement:-

• Minimum congestion.
• Minimum timing DRC's.
• Timing power and area optimization.
• Minimum cell density,pin density and congestion hotspots.

Process in the placement:-

• Course placement:- In floor plan stage we place only macros inside the chi.In placement we place standard cells inside the core.by the course placement outside of standard cells will place inside roughly.

       

(Note:- for just understanding purpose standard cell size was increased.in practical standard cell and rows are too small compare to macros)

• Legalize placement:- By the course placement standard cells overlaps on the rows.To fix this we are doing legalize placement.by this legalize placement all the standard cells are fixed in rows

        

(Note:- for just understanding purpose standard cell size was increased.in practical standard cell and rows are too small compare to macros)

• Congestion analysis:- when available tracks are less then the required tracks then congestion will occur.The congestion range can be estimated by GRC map.

       Congestion reduction techniques:-

       a) Congestion driven placement.

       b) Adjust cell density in congested area(high cell density cause            congestion).

       c) Use proper blockage.

       d) Modify the floor plan design.

• Blockage:- To reduce the congestion we have to use proper blockage.There are three types of blockages hard blockage,soft blockage and partial blockage.By the blockage cells will not overlap.Macro padding and cell padding are the placement blockages.In macro padding the area around the macro is blocked so no std cells will place near to macro.

• HFNS (high fan-out net synthesis):- Fan-out is the maximum number of inputs that a single output of logic gate.To balance the load HFNS is performed.Too many loads will effects the delay numbers and transition time.because load is directly proportional to load.by buffering the HFN the load can be balanced. 

• placement optimization:- It can be done by different options like area recovery,DFT,power,congestion and timing.By using power option we can reduce the static and dynamic power consumpion.By using area recovery we can reduce the cells,power and timing.By scan chain reordering(DFT) we can reduce the routing length. 

Scan chain reordering:- 
                 Scan chain  is used in design for testing.It makes testing easier by setting a group of Flip-flops connecting serially.but in placement stage all the flip-flops are not placed serially (ex:- FF 1 is placed at one corner and FF 2 is placed another corner) but scan chain will connect serially like FF 1 to FF 2 to FF 3.this will leads to increase in routing length and crisscross connection then congestion will increase.In order to decrease this crisscross connection and routing length we are doing scan chain reordering.In this the FF 1 will connect to nearer flip-flop.which will reduce crisscross connections.By the scan chain reordering congestion will reduce but some time it will increase hold time problem in the chain.To over come this buffers inserted in scan path.

Fig 1

Fig 2

Fig 1 shows before scan chain reordering flip-flops are connected serially like FF1-FF2-FF3-FF4. This will increase the routing length and crisscross connections (congestion).
Fig2 shows after scan chain reordering flip-flops are connected nearer by them like FF1-FF3-FF2-FF4. This will decrease the routing length and congestion also decreases.

Power optimization:-
      Now a days most of devices targeted to consume less power because consumers also expecting less power power consumption devices.We have two types of power dissipation.

Static power dissipation:- It is also called leakage power.It can be reduced by replacing LVT cells with HVT cells in a percentage.Because HVT cells have less leakage power.Some architectures will use power gating to reduce static power.

Dynamic power dissipation:- Dynamic power dissipation is due to load and high switching activities.These power can be reduced by reducing the load capacitance,cell sizing,sharing the load.


Outputs of placement:-

• Timing information.
• Congestion report.
• Physical layout information.
• Cell placement location.

CTS

by kamalnadh

                                   CTS
        In this stage we built the clock tree by using inverters and buffers.In the chip clock signal is essential to the flip flops,to give the clock signal from clock source we built the clock tree.It is the process of balancing the clock skew and minimizing insertion delay in order to meet timing and power.

 Before discussing about CTS let see few definitions in CTS.

Aggressor:- A net which creates the effect on nearer net(victim).

Victim:- A net which receives the effect from nearer net(aggressor).

Shielding:- Placing ground net in between aggressor and victim net then voltage discharge on ground net.This will reduce cross-talk.

Cross-talk:- It is the undesirable electric interaction between two or more physical adjust nets due to the capacitance cross coupling.

CTO(clock tree optimization):- It improves the clock skew and clock insertion delay by applying additional optimization. CTO is performed during clock_opt process.

Inputs required for cts:-

• Detailed placement database.
• Target for latency and skew if specified.
• Buffers or inverters for building the clock tree.
• Clock tree DRC's.

Checks before cts:-

• Completed placement.
• Power ground nets - pre routed.
• Acceptable congestion.
• Estimated timing.
• HFNS.

Process:-

      It is a process of inserting buffers and inverters along with the clock path to balance the delay to all clock inputs. Before CTS we treat clock as ideal.If we did't built the clock the skew and insertion delay will increases.This will effects the chip performance.To overcome this we are constructing the clock tree by using inverters and buffers.Below fig shows the structure of before CTS and after CTS.

    Fig:-Before CTS

Fig:-After CTS

Clock tree optimization (CTO):-

It improves the clock skew and clock insertion delay by applying additional optimization. CTO is performed during clock_opt process.The CTO techniques are listed below

Delay insertion:- It will improve hold time.

Buffering:- It will improve setup time.

Buffer relocation:- Reduce skew and insertion delay.

Level adjustment:- Adjust a level of clock pins to a higher or lower

Gate sizing:- It may decrease the delay.

To fix max transition add buffers and to fix max capacitance decrease the net length,cloning.

NDR's:-
Non default rules are applied to reduce the cross-talk and electromigration.NDR's like double spacing,double width shielding.
By applying double spacing cross-talk will reduce.
By applying double width we can avoid electromigration.

Cross-talk:- 

          It is the undesirable electric interaction between two or more physical adjust nets due to the capacitance cross coupling.when two nets are in parallel the electric field of one net is effects the other net which is nearer to it.This called cross-talk effect.

The above fig explain the cross-talk effect.There are two nets running parallel and spacing between the nets are less so capacitance is more.The input of aggressor net inverter is falling signal and the output is raising edge.The input of victim net inverter is raising signal and the output is falling signal.When the rising edge signal is entering into the aggressor net 2nd inverter the charge will stores in the capacitance due to electrical interference at the same time the charge stored in the capacitance will discharge on falling signal of victim net 2nd inverter input.Due to this the falling signal will effect.Here 1st net is creating the effect so that is aggressor and second net receiving effect so that is victim.

Cross-talk reducing techniques:-
a) Increase the spacing between the aggressor and victim nets.
b) Shielding.
c) Maintain the stable supply.
d) Increase the drive strength of cell.
e) Layer jumping.
f) Victim net width increasing then resistance decreases.
g) Guard ring.
h) Cell sizing (up sizing).

CTS exceptions:-

Stop pins:- These are the end point of clock tree and used in calculation and optimization of DRC and clock tree timing(skew,insertion delay).

Float pins:- It's like stop pins with additional delay.

Exclude pins:- It is used only in calculation and optimization of DRC's.It not target skew and insertion delay.


Checklist after cts:-

• Skew report.
• Clock tree report.
• Timing report for setup and hold.
• Power and area report.

CTS goals:-

• Balancing the skew.
• Minimizing insertion delay.
• Minimizing power dissipation.
• Meet the logical DRC's.

STA basic questions and answers

    by Kamalnadh

Q 1. what is STA?
A:  It is a method to determine  the timing constrains of a circuit without simulations.

Q 2. What is setup time?
A: The minimum time required for the data to be stable before the clock edge.

Q 3. What is hold time?

A: The minimum time required for the data to be stable after the clock edge.

Q 4. What is arrival time?
A: This is the time required for data travel through data path.

Q 5. What is required time?
A: It is the time taken for the clock to travel through the clock path.

Q 6. What is slack?

A: It is the difference between the required time and arrival time.

              Slack = Required time­­ - Arrival time

             Setup slack = Required time – Arrival time

             Hold slack = Arrival time – Required time

Q 7.What are the data paths in STA?
A: a) Input port to register.
b) Register to register.
c) Register to output port.
d) Input port to output port.

Q 8. What are the timing constraints (or)exceptions?
 A: a) False path:- It specifies the logic path.
b) multi cycle path:- It specifies the no.of  clock cycles required to propagate data from the start to the end of the path.
c)min/max delay:- It over ride the default setup and hold constraints with specific max &min time values.

Q 9. What is latency (or) clock network delay (or) insertion delay?

A: It is the total delay that a clock signal travels from clock source to clock pin of the flip flop.

Q 10.  What is clock skew?

A: It is the instantaneous difference between the two clock network delays.

Q 11. What is uncertainty?
A: Deviation of clock edge from it’s ideal position.it is caused due to jitters.

Q 12. What is cell delay (or) propagation delay?

A: It is the amount of delay from input to output in a logic path.

Q 13. What is net delay?

A: It is the amount of delay from the output of the cell to the input of the next cell in the timing path.

Q 14. What is drive strength?

A: It is the relative capability to charge/discharge the capacitance present at it’s output (or) It is the capacity of a cell to drive a value to the cell connected to it’s output.It is easy to drive small cell than large.

Q 15. What is clock gating?

A: It is a popular technique used in many synchronous circuits for reducing dynamic power dissipation.It saves power by adding more logic to a circuit to prune the clock tree. 

Q 16. What is OCV (on chip variation)?

A: Flate derate is applied  to make fast path more fast & slow path more slow.Delay vary across a single die due to P,V,T .this to be modeled by scaling the coefficients. 

Q 17. Why we need STA?

A: Sta provides  faster & simpler way of checking & analyzing all the timing parts in the design for any timing violations.

Q 18. What is global skew?

A: It is the difference in the arrival of clock signal at the clock pin of non related flip flops.

Q 19. What is useful skew? 

A: If the clock skew is intentionally added to meet timing then it is called useful skew.

Q 20. What is local skew?

A: It is the difference in the arrival of clock signal at the clock pin of related flip flops.

Q 21. What is derating?
A: Timing derating factor model the effects of varying operating conditions by adjusting the delay values calculated for the individual timing arc of a block.

Q 22. What is CRPR (clock re convergence pessimism removal)?

A: It can be used to remove this pessimism &remove penalty by using the common cell for both launch &capture flip flop.

Q 23. What is recovery time?
A: It is the minimum time that an asynchronous control input pin must be stable after being deserted & before the next clock transition.

Q 24. What is removal time?
A:  It is the minimum time that the asynchronous control input pin must be stable before being deserted & after the previous clock transition.

Q 25. What is the minimum clock pulse width?

A: The amount of time after rising edge of a clock that the clock signal of a clocked device must remain stable.

Q 26. What are the advantages of STA?

A: a) Speed is more.

b) Capacity to handle full chip.
c) Exhaustive timing coverage.
d) Vectors are not required.

e) Suitable for large designs.

Q 27. What are the disadvantages of STA?

A: a) Results are pessimistic .
b) Must define timing requirements/exceptions.

c) Difficulty in handling asynchronous designs.

Q 28. What are the libraries in STA?

A: a) Link lib:- it is a reference path.

b) Target lib:- it is used for optimization.
c) Symbolic lib:- it having symbols of cells(gates).
d) Synthetic lib:- AOI ,OAI combinations.
e) Design ware lib:- provides the connectivity path.

f) Physical lib:- it have shape of cell.

Q 29. What is DRC (design rule check)?

A: It is the area of electronic design automation that determines whether the physical layout of a particular chip layout satisfy a series of recommended parameters called rules.

Q30. What are the types of DRC’s?

A: a) Logical DRC's:- max transition, max capacitance,max fan out.
b) Physical DRC's:- short, open,spacing rules,overlap.

Q 31. What is LVS (layout versus schematic)?

A: LVS is another major check in the physical verification stage.Here you are verifying that whether a particular IC layout correspond to the original schematic or circuit diagram of design.

Q 32. What is cross talk?

A: It is the undesirable electrical interaction between two or more physical adjust nets due to the capacitance cross coupling.

Q 33. What is wire load model?
 A: It is the synthesis phase to account for the physical delay.It contains a lookup table that gives wire resistance ,wire capacitance and the area per unit length.That can be interpolated from the fanout.

Q 34.What is virtual clock?

A: It will help to reduce the timing delay of overall operation.It is the clock which is logically not connected to any port of the design and physically doesn’t exist.It is during optimization.

Q 35.Is zero skew is possible?

A: it is not possible because of all flip flops are not getting the same clock.

Q 36. How to fix setup and hold violations?

A: Fixing setup:-

• Reduce the amount of buffers in the path.
• Replace buffer with 2 inverters.
• Change HVT cells to SVT/LVT cells.
• Increase the drive strength.
• Insert repeaters.
• Adjusting cell position in layout.

 Fixing hold:-

• By adding delay in the path.
• Decreasing the size of certain cells in the data path.

Q 37. What is MMMC (multi mode multi corner)?
A: A view is a combination of a mode & corner that is required for a particular timing check such as setup and hold.

Q 38. What is mode and corner?

A: Mode:- it is a set of clocks,supply voltage,timing constraints and library.it also have sdf.
Corner:- it is defined as a set of libraries characterized for process,voltage, temperature variations.

Q 39. How to minimize the skew?

A: a) Buffering the clock.

     b) Add delay in data path.

     c) Clock reversing.